Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

Abstract: A multi-stage amplifier circuit equalizes an input signal through multiple signal amplification paths. DC gain is kept substantially constant over frequency, while adjustable high-frequency gain provides equalization (e.g., peaking). Various embodiments include a common source topology, a common gate topology, differential signaling topologies, and a topology suitable for stabilizing a voltage supply against high-frequency transient loads. A system may include one or more integrated circuits that may each include one or more instances of the multi-stage amplifier.

Abstract: A chain of bidirectional display driver integrated circuits (DICs). The chain has a beginning and an end, the chain includes a plurality of DICs, each of the plurality of DICs including: a direct data input, a relay data input, and a relay data output. Each of the plurality of DICs is configured to combine data received at the direct data input with a stream of bits received at the relay data input to form combined data, and to transmit the combined data through the relay data output.

Abstract: A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL.

Abstract: A switched equalizer for equalizing the frequency response of a channel with high-frequency attenuation. In one embodiment the differential input of the equalizer is fed to a switch that interchanges the complementary signals at the differential input, changing the sign of the received signal, at each transition of a clock at the Nyquist frequency. The switched signal is filtered by a low-pass filter with positive feedback enhancement at DC gain and digitized by a sense amplifier, and the digital output of the sense amplifier is inverted during every half-cycle of clock at the Nyquist frequency, restoring the sign of the input signal.

Abstract: A serial data transmitter utilizing switching equalization. The transmitter includes a first per-bit switcher configured to invert of every other bit of the stream of bits to form a switched signal; a filter configured to filter the switched signal to form a filtered signal; and a second per-bit switcher configured to invert every other bit of the filtered signal.

Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.

Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.

Abstract: A chain of bidirectional display driver integrated circuits (DICs). The chain has a beginning and an end, the chain includes a plurality of DICs, each of the plurality of DICs including: a direct data input, a relay data input, and a relay data output. Each of the plurality of DICs is configured to combine data received at the direct data input with a stream of bits received at the relay data input to form combined data, and to transmit the combined data through the relay data output.

Abstract: A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.

Abstract: A serial data transmitter utilizing switching equalization. The transmitter includes a first per-bit switcher configured to invert of every other bit of the stream of bits to form a switched signal; a filter configured to filter the switched signal to form a filtered signal; and a second per-bit switcher configured to invert every other bit of the filtered signal.

Abstract: A switched equalizer for equalizing the frequency response of a channel with high-frequency attenuation. In one embodiment the differential input of the equalizer is fed to a switch that interchanges the complementary signals at the differential input, changing the sign of the received signal, at each transition of a clock at the Nyquist frequency. The switched signal is filtered by a low-pass filter with positive feedback enhancement at DC gain and digitized by a sense amplifier, and the digital output of the sense amplifier is inverted during every half-cycle of clock at the Nyquist frequency, restoring the sign of the input signal.

Abstract: A circuit for generating a clock signal formed as a hybrid of a multiplying delay-locked loop (MDLL) and a phase locked loop (PLL). In one embodiment a chain of inverting delay multiplexers is connected in a ring configuration capable of operating as a ring oscillator, with a first delay multiplexer in the ring configured to substitute a feed-in clock signal for the feedback clock generated by the ring oscillator when an edge, either rising or falling, is received at the forwarded clock input. The first delay multiplexer may also be configured to interpolate between the phase of the feedback clock and the phase of the feed-in clock. The interpolation may be based on transistor channel widths and the value of a control signal, and results in behavior intermediate to that of an MDLL and that of a PLL.

Abstract: A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.

Abstract: Described herein is apparatus and system for switching equalization. The apparatus comprises a sampler to sample an input signal; and an attenuator, coupled to the sampler, with a hysteresis associated with the input signal, the hysteresis of the attenuator is configurable to cancel hysteresis of a communication channel coupled to the attenuator.

Abstract: Described herein is apparatus and system for switching equalization. The apparatus comprises a sampler to sample an input signal; and an attenuator, coupled to the sampler, with a hysteresis associated with the input signal, the hysteresis of the attenuator is configurable to cancel hysteresis of a communication channel coupled to the attenuator.