Patents by Inventor Sansaptak W. DASGUPTA

Sansaptak W. DASGUPTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-layer silicon/gallium nitride semiconductor
    Patent number: 10763248
    Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak W. Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun, Patrick Morrow, Valluri R. Rao, Paul B. Fischer, Robert S. Chau
  • MULTI-LAYER SILICON/GALLIUM NITRIDE SEMICONDUCTOR
    Publication number: 20200227396
    Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.
    Type: Application
    Filed: September 24, 2015
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak W. DASGUPTA, Marko RADOSAVLJEVIC, Han Wui THEN, Ravi PILLARISETTY, Kimin JUN, Patrick MORROW, Valluri R. RAO, Paul B. FISCHER, Robert S. CHAU