Abstract: An imaging device includes first and second pixel cells. The first and second pixel cells each include: a photoelectric converter that generates charge; a first charge transfer channel that has a first end electrically connected to the photoelectric converter, and a second end, the charge transfer channel transferring the charge in a direction from the first end toward the second end; a second charge transfer channel that branches from a position of the charge transfer channel, the second charge transfer channel transferring at least a part of the charge; and a charge accumulator that accumulates charge transferred via the second charge transfer channel. Distances from the first end to the position in the direction of the first and second pixel cells are different from each other.

Abstract: In one general aspect, the techniques disclosed here feature an imaging device that includes: a semiconductor substrate; a first pixel cell including a first photoelectric converter in the semiconductor substrate, and a first capacitive element one end of which is electrically connected to the first photoelectric converter; and a second pixel cell including a second photoelectric converter in the semiconductor substrate. An area of the second photoelectric converter is larger than an area of the first photoelectric converter in a plan view.

Abstract: An imaging device includes: pixel cells arranged in a matrix having rows and columns and including first and second pixel cells in one of the columns, each pixel cell comprising a photoelectric converter and a signal detection circuit detecting an electrical signal in the photoelectric converter and outputting an output signal; first and second output signal lines through which the output signals are output from each of the first and second pixel cells, respectively; and first and second feedback circuits that form, for each of the first and second pixel cells, first and second feedback paths negatively feeding back the electrical signals, respectively. The first and second pixel cells are arranged every n rows in the one of the columns where that n is an integer equal to or greater than two, the rows respectively having the first pixel cells being different from those respectively having the second pixel cells.

Abstract: A solid-state imaging device that suppresses streaking includes an imaging region in which unit cells are aligned in matrix, an A/D converter for converting an analog signal generated in the imaging region to a digital signal, and a ramp buffer having an input terminal and an output terminal. Ramp voltage is input to the input terminal, and a reference signal having the ramp voltage is output from the output terminal toward the A/D converter. The A/D converter includes a comparator disposed in each column for comparing an analog signal with a reference signal, and a counter disposed corresponding to the comparator for counting a comparison period of the comparator. The ramp buffer includes a feedback circuit for simultaneously outputting the reference signal to the multiple comparators and controlling the amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the terminal.

Abstract: An imaging device includes a photoelectric converter that generates charge; a first charge transfer channel having a first end electrically connected to the photoelectric converter and a second end, and transferring the charge in a direction from the first end to the second end; a second charge transfer channel diverging from the first charge transfer channel at a first position and transferring a first part of the charge; a third charge transfer channel diverging from the first charge transfer channel at a second position different from the first position in the direction and transferring a part of the second part of the charge; and first and second charge accumulators that accumulate at least a part of the first and second part of the charge respectively. The imaging device does not include a gate that switches between cutoff and transfer of charge, in the first charge transfer channel.

Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

Abstract: A solid-state imaging device that suppresses streaking includes an imaging region in which unit cells are aligned in matrix, an A/D converter for converting an analog signal generated in the imaging region to a digital signal, and a ramp buffer having an input terminal and an output terminal. Ramp voltage is input to the input terminal, and a reference signal having the ramp voltage is output from the output terminal toward the A/D converter. The A/D converter includes a comparator disposed in each column for comparing an analog signal with a reference signal, and a counter disposed corresponding to the comparator for counting a comparison period of the comparator. The ramp buffer includes a feedback circuit for simultaneously outputting the reference signal to the multiple comparators and controlling the amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the terminal.

Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

Abstract: A solid-state imaging device including: a plurality of pixels which are on a same semiconductor substrate and each of which generates a pixel signal; a comparison circuit that is connected to the pixels in each of columns; a D/A conversion circuit that generates a comparison potential and provide the generated comparison potential in common to the comparison circuit in each column; and a D/A conversion circuit output unit provided in a common line for providing the comparison potential to the comparison circuit in each column, wherein the D/A conversion circuit output unit includes: a source follower circuit that is provided to the line and includes a first current source having a transistor, and an amplification transistor having a gate oxide film that is thinner than a gate oxide film of the transistor; and a voltage control circuit that controls a drain-to-source voltage of the amplification transistor.

Abstract: The solid-state imaging device includes a D/A converting circuit generating a reference voltage to be used for an A/D conversion. The D/A converting circuit includes: a voltage generating circuit generating an analog voltage according to a digital signal; a buffer circuit (a resistor ladder upper voltage supplying buffer circuit) which buffers the generated analog voltage, the buffer circuit sampling and holding a bias voltage generated inside the buffer circuit, and outputting the buffered analog voltage using the held bias voltage; an analog signal outputting unit (a resistor ladder unit) outputting the reference voltage according to the inputted digital signal, by receiving an output from the buffer circuit; and a pre-charge amplifier which charges a noise-reducing capacitor in conjunction with the sampling and holding by the buffer circuit, the noise-reducing capacitor being connected to the analog signal outputting unit.

Abstract: A solid-state imaging device including: a plurality of pixels which are on a same semiconductor substrate and each of which generates a pixel signal; a comparison circuit that is connected to the pixels in each of columns; a D/A conversion circuit that generates a comparison potential and provide the generated comparison potential in common to the comparison circuit in each column; and a D/A conversion circuit output unit provided in a common line for providing the comparison potential to the comparison circuit in each column, wherein the D/A conversion circuit output unit includes: a source follower circuit that is provided to the line and includes a first current source having a transistor, and an amplification transistor having a gate oxide film that is thinner than a gate oxide film of the transistor; and a voltage control circuit that controls a drain-to-source voltage of the amplification transistor.