Patents by Inventor Santanu Chaudhuri

Santanu Chaudhuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Setting multiple chip parameters using one IC terminal
    Publication number: 20050099219
    Abstract: A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.
    Type: Application
    Filed: December 15, 2004
    Publication date: May 12, 2005
    Inventors: Sanjay Dabral, Santanu Chaudhuri
  • Low gain phase-locked loop circuit
    Publication number: 20040246057
    Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.
    Type: Application
    Filed: July 13, 2004
    Publication date: December 9, 2004
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
  • Local receive clock signal adjustment
    Publication number: 20040226997
    Abstract: According to some embodiments, a local receive clock signal is adjusted.
    Type: Application
    Filed: March 31, 2003
    Publication date: November 18, 2004
    Inventors: Sanjay Dabral, Richard S. Jensen, Santanu Chaudhuri
  • Low gain phase-locked loop circuit
    Patent number: 6788155
    Abstract: A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 7, 2004
    Assignee: Intel Corporation
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
  • Low gain phase-locked loop circuit
    Publication number: 20040124884
    Abstract: According to some embodiments, a low gain phase-locked loop circuit is provided.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Santanu Chaudhuri, Sanjay Dabral, Karthisha Canagasaby
  • Setting multiple chip parameters using one IC terminal
    Publication number: 20040124875
    Abstract: A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 1, 2004
    Inventors: Sanjay Dabral, Santanu Chaudhuri