Patents by Inventor Santanu PATTANAYAK

Santanu PATTANAYAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928411
    Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Lindsey Makana Kostas, Santanu Pattanayak, Tushit Jain
  • Publication number: 20230267096
    Abstract: The reliability of a data communication link may be analyzed and otherwise maintained by collecting a two-dimensional array representing a functional data eye, and using a convolutional neural network to determine a score of the functional data eye. The determined score may be compared with a threshold, and an action may be initiated based on the result of the comparison.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 24, 2023
    Inventors: Uttkarsh WARDHAN, Vishal GHORPADE, Sanku MUKHERJEE, Madan KRISHNAPPA, Sanath Sreekana BANGALORE, Pankhuri AGARWAL, Santanu PATTANAYAK
  • Publication number: 20230102185
    Abstract: Certain aspects of the present disclosure provide techniques for testing integrated circuit designs based on test cases selected using machine learning models. An example method generally includes receiving a plurality of test cases for an integrated circuit. An embedding data set is generated from the plurality of test cases. A respective embedding for a respective test case of the plurality of test cases generally includes a mapping of the respective test case into a multidimensional space. A plurality of test case clusters is generated based on a clustering model and the embedding data set. A plurality of critical test cases for testing the integrated circuit is selected based on the plurality of test case clusters. The integrated circuit is timed based on the plurality of critical test cases and a hard macro defining the integrated circuit.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Lindsey Makana KOSTAS, Santanu PATTANAYAK, Tushit JAIN
  • Publication number: 20220138613
    Abstract: A method performed by a machine learning system includes generating a set of reward values based on a set of parameter values selected by a machine learning system, each reward value of the set of reward values corresponding to a parameter value of the set of parameter values programmed at a device. The method also includes determining a reward function for maximizing a reward corresponding to a set of parameters of the device based on the set of reward values. The method further includes tuning a parameter of the set of parameters based on the reward function.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 5, 2022
    Inventors: Uttkarsh WARDHAN, Vishal GHORPADE, Sanku MUKHERJEE, Madan KRISHNAPPA, Pankhuri AGARWAL, Sanath Sreekanta BANGALORE, Santanu PATTANAYAK