Patents by Inventor Santanu Sarkar
Santanu Sarkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948984Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.Type: GrantFiled: January 23, 2023Date of Patent: April 2, 2024Assignee: Micron Technology, Inc.Inventors: Ahmed Nayaz Noemaun, Stephen W. Russell, Tao D. Nguyen, Santanu Sarkar
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Publication number: 20230307367Abstract: Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.Type: ApplicationFiled: May 3, 2023Publication date: September 28, 2023Applicant: Micron Technology, Inc.Inventor: Santanu Sarkar
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Patent number: 11682623Abstract: Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.Type: GrantFiled: July 14, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventor: Santanu Sarkar
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Publication number: 20230154989Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.Type: ApplicationFiled: January 23, 2023Publication date: May 18, 2023Applicant: Micron Technology, Inc.Inventors: Ahmed Nayaz Noemaun, Stephen W. Russell, Tao D. Nguyen, Santanu Sarkar
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Patent number: 11600707Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.Type: GrantFiled: May 12, 2020Date of Patent: March 7, 2023Assignee: Micron Technology, Inc.Inventors: Ahmed Nayaz Noemaun, Stephen W. Russell, Tao D. Nguyen, Santanu Sarkar
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Publication number: 20230044518Abstract: In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.Type: ApplicationFiled: October 21, 2022Publication date: February 9, 2023Inventors: Santanu Sarkar, Jay Steven Brown, Shu Qin, Yongjun Jeff Hu, Farrell Martin Good
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Publication number: 20230015046Abstract: Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.Type: ApplicationFiled: July 14, 2021Publication date: January 19, 2023Applicant: Micron Technology, Inc.Inventor: Santanu Sarkar
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Patent number: 11538988Abstract: A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.Type: GrantFiled: March 7, 2019Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Santanu Sarkar, Andrea Gotti, Adam William Saxler
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Patent number: 11527716Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.Type: GrantFiled: March 7, 2019Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Santanu Sarkar, Farrell M. Good
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Publication number: 20220376176Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.Type: ApplicationFiled: August 8, 2022Publication date: November 24, 2022Inventors: Santanu Sarkar, Robert K. Grubbs, Farrell M. Good, Adam W. Saxler, Andrea Gotti
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Patent number: 11508573Abstract: In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.Type: GrantFiled: May 13, 2020Date of Patent: November 22, 2022Assignee: Micron Technology, Inc.Inventors: Santanu Sarkar, Jay Steven Brown, Shu Qin, Yongjun Jeff Hu, Farrell Martin Good
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Patent number: 11444243Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and a metal oxide material adjacent to the stacks of materials. The materials of the stacks comprise one or more chalcogenide materials. The metal oxide material comprises aluminum oxide, aluminum silicate, hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, or a combination thereof and the metal oxide material extends continuously from an upper portion of the one or more stacks of materials to a lower portion of the one or more stacks of materials. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.Type: GrantFiled: October 28, 2019Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Santanu Sarkar, Robert K. Grubbs, Farrell M. Good, Adam W. Saxler, Andrea Gotti
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Patent number: 11424118Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.Type: GrantFiled: January 23, 2020Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Santanu Sarkar, Farrell M. Good
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Publication number: 20220263023Abstract: Apparatus and methods related to forming films on sidewalls of memory cell stacks in memory and logic devices. In one approach, a silicon wafer is held in a chamber of an atomic layer deposition (ALD) reactor. A temperature in the reactor is controlled to a first temperature (e.g., room temperature or below) where a first gas reactant that is provided into the chamber condenses and is adsorbed on the target wafer or substrate. The first reactant or precursor is partly vaporized at a second temperature in the reactor that is greater than the first temperature. A second gas reactant is provided into the chamber. The second gas reactant reacts with the adsorbed portion of the first gas reactant in its activated state. The reaction product is a film on the sidewall of a memory cell stack or logic devices. The foregoing steps are repeated to form a desired thickness of the film.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Inventor: Santanu Sarkar
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Publication number: 20220262628Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Inventors: Santanu Sarkar, Farrell M. Good
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Patent number: 11409502Abstract: Embodiments of the invention are directed to intelligently and dynamically controlling both changes made within EUC applications and the control rules associated with such changes. A similarity index is calculated/assigned for each data entry field (i.e., cell/intersection) and the controls implemented when a changes to data in the entry fields occurs is based on the similarity index. In other embodiments, a change to data entry fields dynamically prompts analysis of the change based on historical approval and/or denial patterns specific to the EUC application, the data entry field(s) and/or the user of the application. In response to the analysis the control rules may be dynamically updated, and applied to the current change. In other embodiments, inputs, such as reviewer's comments, are the basis for determining a need to update existing controls or add new controls associated with data entry field(s) and the conditions associated therewith are determined and applied.Type: GrantFiled: May 6, 2019Date of Patent: August 9, 2022Assignee: BANK OF AMERICA CORPORATIONInventors: Suki Ramasamy, Raghavendra Veerupakshappa, Samson Paulraj, Balasubramanian Bagavathiappan, Timothy Krak, Scott B. Desalvo, Santanu Sarkar, Nikhil Ram, Karrie A. Loatman, Joshua C. Wolfe, Gina L. Tammelleo, Garima Dhir, Kavitha Ganapathi Raman, Phillip Matt Hancock, Kenneth William Schmidt, Jr., Cynthia D. Adams, Christophe M. Marin
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Patent number: 11404267Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein.Type: GrantFiled: December 30, 2019Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Santanu Sarkar, Jerome A. Imonigie, Kent H. Zhuang, Josiah Jebaraj Johnley Muthuraj, Janos Fucsko, Benjamin E. Greenwood, Farrell M. Good
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Publication number: 20210359089Abstract: Some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. A conductive pipe is between the features and substantially parallel to the features. The conductive pipe may be formed within a tube. The tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Applicant: Micron Technology, Inc.Inventors: Ahmed Nayaz Noemaun, Stephen W. Russell, Tao D. Nguyen, Santanu Sarkar
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Publication number: 20210233768Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.Type: ApplicationFiled: January 23, 2020Publication date: July 29, 2021Inventors: Santanu Sarkar, Farrell M. Good
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Publication number: 20210202246Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a structural material for a semiconductor device. The structural material includes an orthosilicate derived oligomer having a number of oxygen (O) atoms each chemically bonded to one of a corresponding number of silicon (Si) atoms and a chemical bond formed between an element from group 13 of a periodic table of elements (e.g., B, Al, Ga, In, and Tl) and the number of O atoms of the orthosilicate derived oligomer. The chemical bond crosslinks chains of the orthosilicate derived oligomer to increase mechanical strength of the structural material, relative to the structural material formed without the chemical bond to crosslink the chains, among other benefits described herein.Type: ApplicationFiled: December 30, 2019Publication date: July 1, 2021Inventors: Santanu Sarkar, Jerome A. Imonigie, Kent H. Zhuang, Josiah Jebaraj Johnley Muthuraj, Janos Fucsko, Benjamin E. Greenwood, Farrell M. Good