Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. A subset of the number of memory storage devices is selected. A subset of the plurality of pins which do not correspond to the subset of the number of memory storage devices and are not part of a memory map of the computer system is selected. Each pin of the subset of the plurality of pins configured with a termination impedance. The subset of the number of memory storage devices is tested.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: Substantial reduction or total elimination of switching transients (glitches) in an information handling system caused by inserting and/or removing hot-pluggable nodes having large power requirements is achieved with a plurality of power supplies having spare power capacity and being configurable into a main power source and an isolated power source. When insertion of a new hot-pluggable node is detected, this newly inserted node is powered from the isolated power source that is not coupled to the other existing operational nodes. When power to the new hot-pluggable node has stabilized and no longer has any detectable transients thereon, the new node is coupled to the main power source which powers the existing nodes of the information handling system. The isolated power source may thereafter be coupled to the main power source for added power supply redundancy. The new node may be detected and made part of or removed from the information handling system without being coupled to the main power source.

Abstract: Substantial reduction or total elimination of switching transients (glitches) in an information handling system caused by inserting and/or removing hot-pluggable nodes having large power requirements is achieved with a plurality of power supplies having spare power capacity and being configurable into a main power source and an isolated power source. When insertion of a new hot-pluggable node is detected, this newly inserted node is powered from the isolated power source that is not coupled to the other existing operational nodes. When power to the new hot-pluggable node has stabilized and no longer has any detectable transients thereon, the new node is coupled to the main power source which powers the existing nodes of the information handling system. The isolated power source may thereafter be coupled to the main power source for added power supply redundancy. The new node may be detected and made part of or removed from the information handling system without being coupled to the main power source.