Abstract: The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.

Abstract: A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the netlist, and wherein both netlists are hierarchical comprising. Aspects of the present invention include comparing the modified netlist with the original netlist outside of the layout tool, and automatically generating at least one change order based on differences found between the two netlists. After the change order is generated, the change order is then applied to the design layout to generate a modified design layout.

Abstract: The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.

Abstract: A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the netlist, and wherein both netlist are hierarchical comprising. Aspects of the present invention include comparing the modified netlist with the original netlist outside of the layout tool, and automatically generating at least one change order based on differences found between the two netlists. After the change order is generated, the change order is then applied to the design layout to generate a modified design layout.

Abstract: Free space on a routed IC is estimated using expanding hierarchical search quadtrees or octrees. Nodes defining rectangular spaces of a layer are created in the tree. Definitions of polygons representing occupied space in the rectangular space are subtracted from a free-space polygon based on the rectangular space. A cost factor is identified for the node, and the process repeats with additional feature polygons until either the cost factor exceeds a maximum or no further feature polygons exist in the layer. If the cost factor exceeds the limit, the node is fractured into child nodes, each defining a quadrant of the parent rectangular space and each containing polygon definitions from the parent node. The process repeats until either the cost factor for each node is not greater than the limit or a dimension of the rectangular space of the node reaches a selected minimum. The nodes define free spaces, which are summed to identify the free space on the IC layer.

Abstract: Free space on a routed IC is estimated using expanding hierarchical search quadtrees or octrees. Nodes defining rectangular spaces of a layer are created in the tree. Definitions of polygons representing occupied space in the rectangular space are subtracted from a free-space polygon based on the rectangular space. A cost factor is identified for the node, and the process repeats with additional feature polygons until either the cost factor exceeds a maximum or no further feature polygons exist in the layer. If the cost factor exceeds the limit, the node is fractured into child nodes, each defining a quadrant of the parent rectangular space and each containing polygon definitions from the parent node. The process repeats until either the cost factor for each node is not greater than the limit or a dimension of the rectangular space of the node reaches a selected minimum. The nodes define free spaces, which are summed to identify the free space on the IC layer.