Patents by Inventor Santhanakrishnan Raman

Santhanakrishnan Raman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7174526
    Abstract: Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 6, 2007
    Assignee: LSI Logic Corporation
    Inventors: Vikram Shrowty, Santhanakrishnan Raman
  • Patent number: 7006962
    Abstract: A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: Saket Goyal, Santhanakrishnan Raman, Prabhakaran Krishnamurthy, Prasad Subbarao, Manjunatha Gowda
  • Patent number: 7007259
    Abstract: A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: Vikram Shrowty, Santhanakrishnan Raman
  • Publication number: 20060026551
    Abstract: Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Inventors: Vikram Shrowty, Santhanakrishnan Raman
  • Publication number: 20050028121
    Abstract: A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Vikram Shrowty, Santhanakrishnan Raman