Patents by Inventor Santhosh Kumar GOWDHAMAN
Santhosh Kumar GOWDHAMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11018686Abstract: A device for monitoring voltage in a battery-operated system, the device including: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder includes: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder includes: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.Type: GrantFiled: June 26, 2020Date of Patent: May 25, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Santhosh Kumar Gowdhaman, Divya Kaur
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Publication number: 20200328756Abstract: A device for monitoring voltage in a battery-operated system, the device comprising: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder comprising: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder comprising: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.Type: ApplicationFiled: June 26, 2020Publication date: October 15, 2020Inventors: Santhosh Kumar Gowdhaman, Divya Kaur
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Patent number: 10735020Abstract: A voltage detector circuit including a ladder selector that includes a first node, a second node and a selector node. The voltage detector circuit also includes a first resistive ladder that includes a first string of resistors coupled between a sensing input node and the first node of the ladder selector and a first set of transistors. An input node of each transistor in the first set of transistors is coupled to a respective intermediate node between two resistors in a subset of resistors in the first string of resistors and an output node of each transistor in the first set of transistors is coupled to a sensing output node. The voltage detector circuit also includes a second resistive ladder that includes a second string of resistors coupled between the sensing input node and the second node of the ladder selector and a second set of transistors.Type: GrantFiled: April 30, 2019Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Santhosh Kumar Gowdhaman, Divya Kaur
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Publication number: 20200076447Abstract: A voltage detector circuit is disclosed. The voltage detector circuit includes a ladder selector that includes a first node, a second node and a selector node. The voltage detector circuit also includes a first resistive ladder that includes a first string of resistors coupled between a sensing input node and the first node of the ladder selector and a first set of transistors. An input node of each transistor in the first set of transistors is coupled to a respective intermediate node between two resistors in a subset of resistors in the first string of resistors and an output node of each transistor in the first set of transistors is coupled to a sensing output node. The voltage detector circuit also includes a second resistive ladder that includes a second string of resistors coupled between the sensing input node and the second node of the ladder selector and a second set of transistors.Type: ApplicationFiled: April 30, 2019Publication date: March 5, 2020Inventors: Santhosh Kumar Gowdhaman, Divya Kaur
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Patent number: 9853657Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.Type: GrantFiled: April 17, 2017Date of Patent: December 26, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eeshan Miglani, Karthikeyan Gunasekaran, Santhosh Kumar Gowdhaman, Shagun Dusad
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Publication number: 20170222658Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.Type: ApplicationFiled: April 17, 2017Publication date: August 3, 2017Inventors: Eeshan Miglani, Karthikeyan Gunasekaran, Santhosh Kumar Gowdhaman, Shagun Dusad
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Patent number: 9660665Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.Type: GrantFiled: August 2, 2016Date of Patent: May 23, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Eeshan Miglani, Karthikeyan Gunasekaran, Santhosh Kumar Gowdhaman, Shagun Dusad
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Publication number: 20170041019Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.Type: ApplicationFiled: August 2, 2016Publication date: February 9, 2017Inventors: Eeshan MIGLANI, Karthikeyan GUNASEKARAN, Santhosh Kumar GOWDHAMAN, Shagun DUSAD