Patents by Inventor Santhosh PATCHAMATLA

Santhosh PATCHAMATLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verification low power collateral generation
    Patent number: 9785732
    Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: October 10, 2017
    Assignee: NetSpeed Systems, Inc.
    Inventors: Vishnu Mohan Pusuluri, Santhosh Patchamatla, Rimu Kaushal, Anup Gangwar, Sailesh Kumar
  • VERIFICATION LOW POWER COLLATERAL GENERATION
    Publication number: 20170228481
    Abstract: Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.
    Type: Application
    Filed: June 12, 2015
    Publication date: August 10, 2017
    Inventors: Vishnu Mohan PUSULURI, Santhosh PATCHAMATLA, Rimu KAUSHAL, Anup GANGWAR, Sailesh KUMAR