Abstract: Aspects of the disclosure provides various systems, apparatuses, and techniques for reducing latencies and power consumption of link training or retraining. In some aspects, the techniques use a specific register to identify the cause of link retraining. Based on the identified reasons of link retraining, the apparatus can selectively skip the initialization of certain redundant lanes of the link. In some aspects, the Universal Chiplet Interconnect Express (UCIe) Link Training and Status State Machine (LTSSM) can be configured to identify whether link retraining is initiated as part of a trainerror or linkerror exit or not. A UCIe device can have a redundant_recovery (RR) register that can be set to different values to identify the cause of link retraining (e.g., due to trainerror/linkerror or not).

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources that include a plurality of logical units (LUs) and at least the particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric of the particular memory resource.

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

Abstract: A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded while the flash memory device is configured to use a shared write buffer. The HCI is also configured to, in response to receiving the notification, perform a remedial action that includes reassigning a portion of a first logical unit (LU).

Abstract: Various embodiments include methods and devices for efficiently recovering from errors that occur in part but not all of a universal chiplet interconnect express (UCIe) link for chiplets of a computing device. Various embodiments may include identifying a first part of a UCIe link in which an error has occurred, and training the first part of the UCIe link in which the error has occurred while maintaining active a second part of the UCIe link in which no error has occurred.

Abstract: Systems and methods for improving security of a Universal Flash Storage (UFS) device during a purge operation. If a purge operation being performed in the UFS device is interrupted prematurely, due to issuance of one or more urgent commands, the UFS device notifies the host processor that the purge operation has been interrupted. After the host processor performs the urgent command(s), it causes the UFS device to resume performance of the purge operation and the host processor delays performance of any other commands that arrive at the command queue (CQ) of the host processor until the resumed purge operation has been completed. Because the purge operation is resumed and completed before the host processor performs any of the other command(s) that have arrived at the CQ, die-level attacks seeking to access unpurged data by sending read commands to the CQ of the host processor are thwarted.

Abstract: The disclosed techniques store certain information of functional modules and lanes to optimize a die-to-die interconnect link. Based on the information, the apparatus can optimize a link width and a multi-module link configuration of the interconnect link. An integrated circuit device includes a first die, a second die, and a die-to-die (D2D) interconnect link connected between the first die and the second die. The D2D interconnect link includes a plurality of lanes grouped into a plurality of modules. The apparatus maintains a training result of the D2D interconnect link based on the training of the D2D interconnect link, the training result including one or more link configurations of the plurality of modules. The apparatus selects a link configuration of the one or more link configurations to configure the D2D interconnect link including one or more of the plurality of modules.

Abstract: Systems and methods improve write performance of a UFS device comprising N logical units (LUNs) and N write buffers (WBs), where N is a positive integer. Each WB is mapped to a respective LUN. Each WB has a respective WB lifetime estimate value and a respective WB lifetime threshold (TH) value. A determination is made as to whether the WB lifetime estimate value associated with at least a first WB of the N WBs is equal to or is greater than the respective WB TH value, and if so, the first WB is remapped to a second LUN of the N LUNs and a second WB of the N WBs is remapped to the first LUN. The remapping is based at least in part on the WB lifetime estimate value associated with the second WB indicating that the second WB has more lifetime remaining than the first WB.

Abstract: Various embodiments include methods and devices for implementing Universal Chiplet Interconnect Express (UCIe) link configuration for multi-module chiplets of a computing device. Embodiments may include transitioning a UCIe link in an active state having a first sideband that is active to the UCIe link in a reset state, and initializing at least one sideband for the UCIe link that is a different functional sideband of a multi-module chiplet than the first sideband following the reset state of the UCIe link. Embodiments may include reading sideband data configured to represent a functional sideband of the multi-module chiplet, and initializing the functional sideband as the at least one sideband. Embodiments may include reading sideband data configured to represent at least two functional sidebands of the multi-module chiplet, and initializing at least one functional sideband of the at least two functional sidebands as the at least one sideband.

Abstract: Aspects of the disclosure provides various systems, apparatuses, and techniques for reducing latencies and power consumption of link training or retraining. In some aspects, the techniques use a specific register to identify the cause of link retraining. Based on the identified reasons of link retraining, the apparatus can selectively skip the initialization of certain redundant lanes of the link. In some aspects, the Universal Chiplet Interconnect Express (UCIe) Link Training and Status State Machine (LTSSM) can be configured to identify whether link retraining is initiated as part of a trainerror or linkerror exit or not. A UCIe device can have a redundant_recovery (RR) register that can be set to different values to identify the cause of link retraining (e.g., due to trainerror/linkerror or not).

Abstract: A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example a memory device includes a memory controller to initiate a write buffer flush operation. A bus interface is coupled to a main memory and to a write buffer to receive a write command from a host during the write buffer flush operation. The memory controller initiates the write buffer flush operation, suspends the write buffer flush operation in response to the write command, sends a last flushed address of the write buffer from the memory device to the host through the bus interface, and unmaps a portion of the write buffer using the last flushed address.

Abstract: Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.

Abstract: Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

Abstract: Various embodiments include methods and devices for implementing a Peripheral Component Interconnect Express (PCIe) link configuration by a computing device. Embodiments may include selecting, by a PCIe device, a predetermined PCIe link speed based on a PCIe link configuration mode of a PCIe system of a plurality of PCIe link configuration modes of the PCIe system, and selecting, by the PCIe device, a PCIe link width of one lane for configuring the PCIe link. Embodiments may include selecting a PCIe link speed level lower than a current PCIe link speed in response to a reliability indicator exceeding a reliability threshold for a first PCIe link configuration mode. Embodiments may include selecting a maximum PCIe link speed for the PCIe link for a second PCIe link configuration mode. Embodiments may include increasing the PCIe link width in response to a requested bandwidth exceeding a configuration bandwidth of the PCIe link.

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support queued current level adjustment in a flash memory system. In a first aspect, a method of accessing data in a flash memory system includes receiving, at a memory controller of a memory system from a host device, a first request to adjust a current level of a memory module of the memory system, storing, by the memory controller, an indication of the first request in a register associated with the memory controller, and transmitting, to the host device, an indication that the first request is pending. Other aspects and features are also claimed and described.

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for optimizing usage of a shared write booster buffer to extend lifetime.