Patents by Inventor Santhosh UMESH

Santhosh UMESH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamically tunable heterogeneous latencies in switch or router chips
    Patent number: 9722954
    Abstract: A device with dynamically tunable heterogeneous latencies includes an input port configured to receive a packet via a network, and a processing module configured to determine multiple values corresponding to a number of qualifying parameters associated with the packet. The processing module may use the values to generate a selector value and may allocate a latency mode to the packet based on the selector value.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: August 1, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Vijay Anand Purushothaman, Sandeep Kumar Relan, Santhosh Umesh, Santosh Kalluthirike Janardhan, Tarun Kumar Varshney, Mohan Venkatachar Kalkunte, Venkateshwar Buduma, Samir Kishore Sanghani
  • Scalable and predictive packet processing
    Patent number: 9288144
    Abstract: A system for scalable and predictive packet processing may include a memory and a processor. The memory may be configured to store packet processing results performed on a packet. The processor may be configured to apply the stored packet processing results to subsequently received packets that have the same flow identifier as the processed packet without performing ingress packet processing on the subsequent packets.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Broadcom Corporation
    Inventors: Santhosh Umesh, Tarun Kumar Varshney, Vijay Anand Purushothaman, Mohan Kalkunte, Santosh Kalluthirike Janardhan
  • SCALABLE AND PREDICTIVE PACKET PROCESSING
    Publication number: 20150117455
    Abstract: A system for scalable and predictive packet processing may include a memory and a processor. The memory may be configured to store packet processing results performed on a packet. The processor may be configured to apply the stored packet processing results to subsequently received packets that have the same flow identifier as the processed packet without performing ingress packet processing on the subsequent packets.
    Type: Application
    Filed: November 27, 2013
    Publication date: April 30, 2015
    Applicant: Broadcom Corporation
    Inventors: Santhosh UMESH, Tarun Kuma VARSHNEY, Vijay Anand PURUSHOTHAMAN, Mohan KALKUNTE, Santosh Kalluthirike JANARDHAN
  • DYNAMICALLY TUNABLE HETEROGENEOUS LATENCIES IN SWITCH OR ROUTER CHIPS
    Publication number: 20150110132
    Abstract: A device with dynamically tunable heterogeneous latencies includes an input port configured to receive a packet via a network, and a processing module configured to determine multiple values corresponding to a number of qualifying parameters associated with the packet. The processing module may use the values to generate a selector value and may allocate a latency mode to the packet based on the selector value.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 23, 2015
    Applicant: BROADCOM CORPORATION
    Inventors: Vijay Anand PURUSHOTHAMAN, Sandeep Kumar RELAN, Santhosh UMESH, Santosh Kalluthirike JANARDHAN, Tarun Kumar VARSHNEY, Mohan Venkatachar KALKUNTE, Venkateshwar BUDUMA, Samir Kishore Sanghani