Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.

Abstract: An electronic system includes a first LC oscillator connected to a first general-purpose input/output (GPIO) circuit and a second LC oscillator connected to a second GPIO circuit. A threshold generator is coupled to an input of the comparator. A control circuit is configured to control a measurement phase comprising a first capture phase and a second capture phase. A microcontroller is coupled to the control circuit and a power management circuit is configured to switch-off the microcontroller following activation of the control circuit by the microcontroller. The control circuit is configured to control the application of an excitation signal to the each oscillator via the respective GPIO circuit, control the GPIO circuit so that oscillations of the oscillator are provided to the comparator, and count, based on an output of the comparator, a number of oscillations in the oscillator exceeding a threshold output by the threshold generator.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/output register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/output register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a commands, and resumes the normal operating mode in response to a wake-up events.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Abstract: A processing system comprising a first sub-circuit configured to be powered by a first supply voltage and a second sub-circuit configured to be powered by a second supply voltage. The first sub-circuit comprises a general-purpose input/out register. The second sub-circuit comprises: a storage circuit configured to selectively store configuration data from the general-purpose input/out register; an input/output interface, at least one peripheral and a selection circuits to exchange signals of the peripherals, and the stored configuration data with the input/output interface. A power management circuit is configured to manage a normal operating mode, and a low-power mode during which the configuration data are maintained stored and the first sub-circuit is switched off. The power management circuit activates the low-power mode in response to receiving a command, and resumes the normal operating mode in response to a wake-up event.

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns, an oscillator configured to generate a clock signal for the FSM, a first signal path activatable between the first slave address pin and the FSM, and a second signal path activatable between the FSM and the second slave address pin.

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.

Abstract: A circuit includes: a communication interface configured to receive data; a plurality of output terminals; a bank of input registers coupled to the communication interface; a bank of buffer registers; a bank of output registers; a signal generator configured to generate a plurality of output signals based on respective registers of the bank of output registers at respective output terminals; and a conversion stage configured to: when data is received by the bank of input registers from the communication interface, sequentially convert content of the input registers of the bank of input registers and store the converted content into corresponding buffer registers of the bank of buffer registers based on a conversion function, and when the conversion stage finishes storing the converted content into the buffer registers, simultaneously copy content from the buffer registers into corresponding output registers of the bank of output registers.

Abstract: A circuit includes a set of LED driver devices and a controller including a set of nodes coupled to a first slave address pin and a second slave address pin in each LED driver devices in the set of LED driver devices. Each LED driver device includes: a finite state machine (FSM) configured to generate LED drive PWM-modulated signal patterns; an oscillator configured to generate a clock signal for the FSM; a first signal path activatable between the first slave address pin and the FSM; and a second signal path activatable between the FSM and the second slave address pin.

Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.

Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.

Abstract: A battery charger which includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery, at least one output terminal and an electrical path between the battery terminal and the output terminal, at least one device for the detection of one alarm condition of the battery or the battery charger. The battery charger includes circuitry configured to enable the at least one detection device at timing intervals when the battery supplies the at least one output terminal.

Abstract: A battery charger includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery and at least one output terminal, a switch arranged in the electrical path between the battery terminal and at least one output terminal, an element configured to store an information representative of an alarm condition of the battery and to open the switch when the alarm condition occurs, with the supply signal being absent and the battery supplying the at least one output terminal, and to close the switch when the supply signal is received at the input supply terminal.

Abstract: A battery charger which includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery, at least one output terminal and an electrical path between the battery terminal and the output terminal, at least one device for the detection of one alarm condition of the battery or the battery charger. The battery charger includes circuitry configured to enable the at least one detection device at timing intervals when the battery supplies the at least one output terminal.

Abstract: A battery charger includes an input supply terminal configured to receive a supply signal, a battery terminal configured to be connected to a battery and at least one output terminal, a switch arranged in the electrical path between the battery terminal and at least one output terminal, an element configured to store an information representative of an alarm condition of the battery and to open the switch when the alarm condition occurs, with the supply signal being absent and the battery supplying the at least one output terminal, and to close the switch when the supply signal is received at the input supply terminal.