Patents by Inventor Santi Nunzio Antonino Pagano

Santi Nunzio Antonino Pagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170278552
    Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Antonino Conte, Mario Micciche', Santi Nunzio Antonino Pagano
  • Patent number: 8570813
    Abstract: The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: October 29, 2013
    Assignee: STMicroelectronics S.R.L.
    Inventors: Carmelo Ucciardello, Antonino Conte, Santi Nunzio Antonino Pagano
  • Patent number: 8405450
    Abstract: A charge pump including first and a second charge-pump stages electrically coupled, four pump capacitors connected between two enable terminals and four internal nodes, two pump transistors connected to the pump capacitors and to the internal nodes, and having respective control terminals, two biasing capacitors, connected between the control terminals and the enable terminals, and an equalization circuit connected between the control terminals and structured to limit the voltage between the control terminals within a first range of values.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: March 26, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Carmelo Ucciardello, Antonino Conte, Santi Nunzio Antonino Pagano
  • Patent number: 8390366
    Abstract: A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: March 5, 2013
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.l.
    Inventors: Santi Nunzio Antonino Pagano, Francesco La Rosa, Alfredo Signorello
  • Publication number: 20120250421
    Abstract: The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages.
    Type: Application
    Filed: March 15, 2012
    Publication date: October 4, 2012
    Applicant: STMicroelectronics S.r.l.
    Inventors: Carmelo UCCIARDELLO, Antonino Conte, Santi Nunzio Antonino Pagano
  • Publication number: 20110128070
    Abstract: A charge pump having a supply terminal, for receiving a supply voltage, and an output terminal, for supplying an output voltage. The charge pump has a control block including a comparator having a first comparison input, for receiving the supply voltage, a second comparison input, for receiving the output voltage, and a comparison output, for generating a pump-switch-off signal depending upon a comparison between the input voltage and the output voltage; and a switch controlled in switching off by the pump-switch-off signal and configured for switching off the charge pump circuit. The control block has an activation input for receiving an activation signal that has a plurality of pulses and repeatedly activates the comparator-circuit block.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics S.r.I.
    Inventors: Santi Nunzio Antonino Pagano, Francesco La Rosa, Alfredo Signorello
  • Publication number: 20110068857
    Abstract: A charge pump including first and a second charge-pump stages electrically coupled, four pump capacitors connected between two enable terminals and four internal nodes, two pump transistors connected to the pump capacitors and to the internal nodes, and having respective control terminals, two biasing capacitors, connected between the control terminals and the enable terminals, and an equalization circuit connected between the control terminals and structured to limit the voltage between the control terminals within a first range of values.
    Type: Application
    Filed: September 15, 2010
    Publication date: March 24, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Carmelo Ucciardello, Antonino Conte, Santi Nunzio Antonino Pagano
  • Patent number: 7617407
    Abstract: A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by: maintaining the in a stand-by mode when no memory read/write commands are to be executed, and if any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: November 10, 2009
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Santi Carlo Adamo, Rosalino Critelli, Santi Nunzio Antonino Pagano, Martino Quattrocchi