Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: A CMOS reference current source comprises two circuit branches connected in parallel between supply terminals. The first circuit branch includes a series connection of a bias current source (MP1) and a first MOS transistor (MN1) of a first conductivity type. The second circuit branch includes a series connection of a diode-connected MOS transistor (MP2) of a second conductivity type, a second MOS transistor (MN2) of the first conductivity type and a third MOS transistor (MN3) of the first conductivity type. The first MOS transistor (MN 1) of the first conductivity type has its gate connected to the drain of the third MOS transistor (MN3) of the first conductivity type. The second MOS transistor (MN2) of the first conductivity type has its gate connected to the drain of the first MOS transistor (MN1) of the first conductivity type. The third MOS transistor (MN3) the first conductivity type has its gate connected to a bias source (MN4).

Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.

Abstract: An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.

Abstract: A N-bit segmented digital to analog converter (DAC) adapted to provide an analog signal output on the basis of a digital input code, the DAC being formed from a plurality of individual segments, the segments being selectively combined to effect the output from the DAC determined by the input and wherein the number of segments is given by 2N?1+x where x is greater or equal to one, and at least one of the segments has a weighting less than that of the least significant bit (LSB) of the overall DAC.