Abstract: Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.

Abstract: A method and device for handling Ethernet frame signals in a SDH/SONET network, the SDH/SONET network comprising network elements or nodes and fiber connections connecting the network elements, the method being characterized by the step of defining a new layer/network over the SDH/SONET network in order to manage the Ethernet signals over the SDH/SONET network, the new layer/network using the resources of SDH/SONET network in such a way as to optimize the provided services and the performances with reference to this specific type of transport.

Abstract: Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.

Abstract: Improved interface system for synchronous hierarchy telecommunication networks, in particular SDH networks, comprising a high frequency backpanel function, said system comprising at least a central board and one or more input/output peripheral board apt to exchange data frames and control bytes. According to the invention, the data frames contain control bytes and said data frames are bitwise converted before being exchanged between the peripheral boards and the central board.

Abstract: A delay-locked loop circuit (DLL) includes a delay line with a delay which can be varied in a controlled manner to delay a periodic input signal having a period T, and a control circuit for controlling the delay line to lock the delay to the period T. The delay line supplies to the control circuit a plurality of periodic signals each delayed relative to the periodic input signal by a respective fraction of the delay. The control circuit includes a sequence-detector circuit which can periodically detect in the delayed signals characteristic sequences of digital values indicative of the delay. The control circuit can bring about a reduction or an increase in the delay for locking to the period T based upon the detected types of characteristic sequences.