Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

Abstract: A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed.

Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract: A circuit for providing voltage level shifting in an integrated circuit includes an inverter having an input coupled to receive an input signal having a first voltage level; an output stage having a first transistor coupled in series with a second transistor, and an output node between the first transistor and the second transistor generating an output signal having a second voltage level. A gate of the second transistor is coupled to an output of the inverter. A pull-up transistor is coupled between a reference voltage having the second voltage level and a gate of the first transistor. A switch is coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the gate of the first transistor. A method of providing voltage level shifting in an integrated circuit is also disclosed.

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract: A circuit for processing data in an integrated circuit device comprises a selection circuit; a first register coupled to a first output of the selection circuit; a second register implemented as a latch and coupled to a second output of the selection circuit; and a signal line coupled between the output of the first register and an input of the selection circuit. The selection circuit enables the coupling of an output signal of the first register to an input of the second register. A method of processing data in an integrated circuit device is also disclosed.

Abstract: Emulating power gating includes identifying an isolation circuit having a first input coupled to an output of a first power domain, a second input coupled to an isolation signal, and an output coupled to an input of a second power domain; removing a power gate circuit configured to selectively decouple the first power domain from a power supply responsive to a power gate signal; and decoupling the first input of the isolation circuit from the output of the first power domain. A power gate emulation circuit is inserted using a processor. The power gate emulation circuit is coupled to the isolation signal, the power gate signal, and the output of the first power domain.

Abstract: In one example, a programmable integrated circuit (IC) includes a first logic tile in a first power domain having a first local voltage. The first logic tile includes a driver operable to use the first local voltage to output a signal having a logic-level referenced to the first local voltage. The first logic tile further includes a level-shifter coupled to receive the signal from the driver and operable to output a level-shifted signal having a logic-level referenced to a global handshaking voltage. The programmable IC further includes a second logic tile in a second power domain having a second local voltage, the second logic tile including a receiver operable to use the second local voltage to receive the level-shifted signal. The global handshaking voltage is at least as high as the first local voltage and at least as high as the second local voltage.

Abstract: A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.

Abstract: An apparatus relating generally to an analog multiplexer is disclosed. In such an apparatus, the analog multiplexer has first select circuits and at least one second select circuit. The first select circuits have respective input nodes and output nodes. The output nodes are all coupled to one another to provide an output node of the analog multiplexer. The first select circuits are coupled to a first supply voltage of a first supply domain. The at least one second select circuit is coupled to a second supply voltage of a second supply domain different from the first supply domain. The at least one second select circuit has an input port and an output port. The output port is coupled to an input node of the input nodes.