Abstract: A hardware accelerator for neural network applications can include an image-to-column block and a general matrix-matrix multiplication (GEMM) block. The image-to-column block includes an input controller coupled to receive an input feature map from a memory block; a series of patch units configured in a ring network and coupled to the input controller to receive new elements of the input feature map; and an output controller coupled to receive each output patch from the series of patch units. The GEMM block can be a dynamically reconfigurable unit that can be configured as a tall array or individual square arrays. The described hardware accelerator can handle sparsity in both the feature map inputs (output from the image-to-column block) and the filter/weight inputs to the GEMM block.