Patents by Inventor Santosh Narayanan
Santosh Narayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9319325Abstract: A method, an apparatus and/or a system to regulate yellow traffic in a network is provided. In one embodiment, the method includes quantifying, an extent of violation of a transmission rate of a data traffic relative to a committed bandwidth profile in a network. The data traffic is generated through a client device coupled to the network. The method also includes regulating, a volume of the data traffic associated with a particular level of compliance relative to the committed bandwidth profile, at an edge node of the network, based on the quantification. The committed bandwidth profile specifies an average rate of committed and excess data traffic generated by the client device. The particular level of compliance is characterized by the transmission rate exceeding a committed information rate and lying within a peak information rate. The peak information rate is maximum allowable rate of admission of frames into the network.Type: GrantFiled: August 24, 2010Date of Patent: April 19, 2016Assignee: Intel CorporationInventors: Govindarajan Mohandoss, Santosh Narayanan, Vijaya Bhaskar Kommineni, Rayesh Kashinath Raikar
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Patent number: 9270593Abstract: Aspects of the disclosure pertain to a system and method for providing prediction based, fast routing of IP flows. A hash table-based mechanism is implemented by the system such that classification information obtained and/or utilized for a first packet of an IP flow is applied to subsequent packets of the IP flow, thereby promoting packet processing efficiency for the flow.Type: GrantFiled: April 3, 2014Date of Patent: February 23, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Benzeer B. Pazhayakath, Vishal D. Ajmera, Santosh Narayanan
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Patent number: 9065756Abstract: Aspects of the disclosure pertain to a system and method for providing fast and efficient flushing of a forwarding database in a network processor. The present disclosure provides a deterministic mechanism to implement a flush operation for flushing the forwarding database. A dual FDB approach, a means for switching from one FDB to another in the event of a failure, and FDB flush operation as a background task are key features of this disclosure. The effective time for completing the flush operation is within a sub-50 millisecond time frame and is independent of the number of entries in the forwarding database. The flush operation may be performed using software.Type: GrantFiled: January 9, 2013Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Vishal D. Ajmera, Santosh Narayanan, Benzeer B. Pazhayakath
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Patent number: 8930604Abstract: In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of the node. Each different event category can be assigned its own scale factor, where the available (i.e., currently unused) capacity of the hardware interrupt buffer is allocated based on those programmed scale factors. If the node determines to handle the detected event using the hardware interrupt buffer, then the node stores a hardware interrupt corresponding to the detected event in the hardware interrupt buffer. Otherwise, the node handles the detected event using a fallback action.Type: GrantFiled: July 17, 2012Date of Patent: January 6, 2015Assignee: LSI CorporationInventors: Benzeer Bava Arackal Pazhayakath, Santosh Narayanan
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Publication number: 20140334491Abstract: Aspects of the disclosure pertain to a system and method for providing prediction based, fast routing of IP flows. A hash table-based mechanism is implemented by the system such that classification information obtained and/or utilized for a first packet of an IP flow is applied to subsequent packets of the IP flow, thereby promoting packet processing efficiency for the flow.Type: ApplicationFiled: April 3, 2014Publication date: November 13, 2014Applicant: LSI CorporationInventors: Benzeer B. Pazhayakath, Vishal D. Ajmera, Santosh Narayanan
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Publication number: 20140298148Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.Type: ApplicationFiled: June 16, 2014Publication date: October 2, 2014Applicant: LSI CorporationInventors: Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda
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Patent number: 8792511Abstract: A system and method for allocating memory locations in a buffer memory system is described. The system includes a plurality of memory locations for storage and a controller. The controller controls the storage and retrieval of data from the plurality of memory locations and allocate a first portion of the memory locations to a first buffer, wherein the remaining portion of the memory locations defines a second portion. The controller allocates a portion of the second portion to a second buffer and the remaining portion of the second portion defines a third portion. The controller reserves a portion of the third portion for assignment to the second buffer, wherein, the second buffer is assigned a higher priority over the first buffer. The controller selectively allocates one or more memory locations of the third portion to the first buffer or to the second buffer.Type: GrantFiled: April 18, 2011Date of Patent: July 29, 2014Assignee: LSI CorporationInventors: Rayesh Raikar, Santosh Narayanan, Govidarajan Mohandoss, Ranjith Kumar Kotikalaoudi
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Patent number: 8782504Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.Type: GrantFiled: April 11, 2012Date of Patent: July 15, 2014Assignee: LSI CorporationInventors: Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda
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Publication number: 20140192633Abstract: Aspects of the disclosure pertain to a system and method for providing fast and efficient flushing of a forwarding database in a network processor. The present disclosure provides a deterministic mechanism to implement a flush operation for flushing the forwarding database. A dual FDB approach, a means for switching from one FDB to another in the event of a failure, and FDB flush operation as a background task are key features of this disclosure. The effective time for completing the flush operation is within a sub-50 millisecond time frame and is independent of the number of entries in the forwarding database. The flush operation may be performed using software.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: LSI CORPORATIONInventors: Vishal D. Ajmera, Santosh Narayanan, Benzeer B. Pazhayakath
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Publication number: 20140025856Abstract: In a data network, a node determines whether to handle data-dependent events using the node's hardware interrupt buffer or instead using an available fallback action. The node classifies each detected event as being one of a plurality of different categories of events and determines, based on the classified category, whether to handle the detected event using the hardware interrupt buffer of the node. Each different event category can be assigned its own scale factor, where the available (i.e., currently unused) capacity of the hardware interrupt buffer is allocated based on those programmed scale factors. If the node determines to handle the detected event using the hardware interrupt buffer, then the node stores a hardware interrupt corresponding to the detected event in the hardware interrupt buffer. Otherwise, the node handles the detected event using a fallback action.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: LSI CORPORATIONInventors: Benzeer Bava Arackal Pazhayakath, Santosh Narayanan
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Publication number: 20130275843Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Applicant: LSI CorporationInventors: Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda
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Publication number: 20120327948Abstract: In one embodiment, a network processor services a plurality of queues having data using weighted round robin scheduling. Each queue is assigned an initial weight based on the queue's priority. During each cycle, an updated weight is generated for each queue by adding the corresponding initial weight to a corresponding previously generated decremented weight. Further, each queue outputs as many packets as it can without exceeding its updated weight. As each packet gets transmitted, the updated weight is decremented based on the number of blocks in that packet. If, after those packets are transmitted, the decremented weight is still positive and the queue still has data, then one more packet is transmitted, no matter how many blocks are in the packet. When a decremented weight becomes negative, the weights of the remaining queues are increased to restore the priorities of the queues as set by the initial weights.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Applicant: LSI CorporationInventors: Govindarajan Mohandoss, Santosh Narayanan, Rayesh Kashinath Raikar, Prabhakar Ballapalle
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Publication number: 20120263181Abstract: A system and method for allocating memory locations in a buffer memory system is described. The system includes a plurality of memory locations for storage and a controller. The controller controls the storage and retrieval of data from the plurality of memory locations and allocate a first portion of the memory locations to a first buffer, wherein the remaining portion of the memory locations defines a second portion. The controller allocates a portion of the second portion to a second buffer and the remaining portion of the second portion defines a third portion. The controller reserves a portion of the third portion for assignment to the second buffer, wherein, the second buffer is assigned a higher priority over the first buffer. The controller selectively allocates one or more memory locations of the third portion to the first buffer or to the second buffer.Type: ApplicationFiled: April 18, 2011Publication date: October 18, 2012Inventors: Rayesh RAIKAR, Santosh NARAYANAN, Govidarajan MOHANDOSS, Ranjith Kumar KOTIKALAOUDI
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Publication number: 20120051218Abstract: A method, an apparatus and/or a system to regulate yellow traffic in a network is provided. In one embodiment, the method includes quantifying, an extent of violation of a transmission rate of a data traffic relative to a committed bandwidth profile in a network. The data traffic is generated through a client device coupled to the network. The method also includes regulating, a volume of the data traffic associated with a particular level of compliance relative to the committed bandwidth profile, at an edge node of the network, based on the quantification. The committed bandwidth profile specifies an average rate of committed and excess data traffic generated by the client device. The particular level of compliance is characterized by the transmission rate exceeding a committed information rate and lying within a peak information rate. The peak information rate is maximum allowable rate of admission of frames into the network.Type: ApplicationFiled: August 24, 2010Publication date: March 1, 2012Applicant: LSI CORPORATIONInventors: Govindarajan Mohandoss, Santosh Narayanan, Vijaya Bhaskar Kommineni, Rayesh Kashinath Raikar