Abstract: Described herein is a system and method for audio visual synchronization. The picture are displayed by receiving an identifier, said identifier associated with a frame buffer storing a picture; extracting a presentation time stamp associated with the picture, wherein the picture is associated with a time stamp; comparing a local time clock value to the presentation time stamp; determining that the picture is mature for presentation if the presentation time stamp exceeds the local time clock value by less than a first predetermined threshold; and determining that the picture is mature for presentation if the local time clock value exceeds the presentation time stamp by less than a second predetermined threshold.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory are off-chip.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

Abstract: Disclosed are various embodiments for displaying pictures at high speed. In one embodiment, a system includes a buffer for storing parameters associated with a predetermined number of the pictures during a video display period. The system further includes a video decoder for decoding particular ones of the predetermined number of the pictures. The predetermined ones are either reference pictures or pictures that are to be displayed at high speed. The pictures that are displayed in high speed at each display interval have a constant time-lapse between the pictures that are displayed in high speed at the next display interval.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

Abstract: A system, method, and apparatus for providing display parameters from the decode process to the display process are presented herein. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images as well as the parameters and stores each image in a separate image buffer. Additionally, the decode process stores the parameters which facilitate the display process in a buffer descriptor structure associated with the image buffer. The display process uses the parameters stored in the buffer descriptor structure during the display process.

Abstract: Presented herein are systems and methods for slow motion and high speed for digital video. In one embodiment, there is presented a method for displaying pictures. The method comprises displaying a top field from a particular picture, for a predetermined number of consecutive vertical synchronization pulses; and displaying a bottom field from the particular picture for the predetermined number of consecutive vertical synchronization pulses.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory are off-chip.

Abstract: Disclosed herein are debugging tool(s) for profiling the frequency of execution of certain instructions in a host operation. The debugging tool causes interrupts to occur at random time intervals and records the address of the program counter at each interrupt. A profile is developed that indicates the frequency of execution of certain instructions after a statistically significant number of interrupts.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory are off-chip.

Abstract: Presented herein is a system and method for pause and picture advance. In one embodiment, there is presented a method for displaying pictures. The method comprises displaying a first picture at a first vertical synchronization signal; receiving a particular input between the first vertical synchronization signal and a second vertical synchronization signal, the second vertical synchronization signal coming after the first vertical synchronization signal; displaying a second picture at the second vertical synchronization signal; and preventing overwriting of the second picture.

Abstract: Presented herein are systems and methods for pause and freeze functions for digital video streams. A particular picture is displayed for a plurality of video display periods. A next picture is displayed at the video display period immediately following the plurality of video display periods, the next picture immediately following the particular picture in a display order. A system clock reference is loaded with a time stamp associated with the next picture when displaying the next picture.

Abstract: Presented herein are systems and methods for slow motion and high speed for digital video. In one embodiment, there is presented a method for displaying pictures. The method comprises displaying a top field from a particular picture, for a predetermined number of consecutive vertical synchronization pulses; and displaying a bottom field from the particular picture for the predetermined number of consecutive vertical synchronization pulses.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory are off-chip.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

Abstract: A system, method, and apparatus for decoding and displaying images utilizing two processors and two memory units. The decode process receives images which are encoded according to a predetermined standard. Included with the encoded images are parameters which facilitate the decode and display processes. The decode process decodes the encoded images and the encoded parameters and stores each image in a separate image buffer, and each set of associated parameters in a buffer descriptor structure associated with the image buffer. The decode process is carried on by the first processor. The display process utilizes the parameters associated with the image to determine the appropriate display order for each image, and then display the image accordingly on a display device, based on the associated parameters. The first processor carries on the display of the image on the display device. The second processor determines the display order for the images. The second processor and the second memory can be off-chip.

Abstract: Aspects of the present invention are directed to a system, method, and apparatus for annotating decompressed frames from a video sequence. In one embodiment, a data structure comprising a compressed representation of a first frame and a set of parameters is received. The first frame is decompressed and a graphic displaying at least one of the parameters is created. The graphic displaying at least one of the parameters is annotated to the decompressed first frame.

Abstract: Described herein is a system and method for audio visual synchronization. The picture are displayed by receiving an identifier, said identifier associated with a frame buffer storing a picture; extracting a presentation time stamp associated with the picture, wherein the picture is associated with a time stamp; comparing a local time clock value to the presentation time stamp; determining that the picture is mature for presentation if the presentation time stamp exceeds the local time clock value by less than a first predetermined threshold; and determining that the picture is mature for presentation if the local time clock value exceeds the presentation time stamp by less than a second predetermined threshold.

Abstract: Presented herein is a system, method, and apparatus for displaying a plurality of video sequences in real-time while reducing the required buffer memory. In an exemplary embodiment, a decoder system is presented that decodes and presents two video sequences, with three frame buffers per video sequence.

Abstract: Disclosed herein are debugging tool(s) for profiling the frequency of execution of certain instructions in a host operation. The debugging tool causes interrupts to occur at random time intervals and records the address of the program counter at each interrupt. A profile is developed that indicates the frequency of execution of certain instructions after a statistically significant number of interrupts.