Patents by Inventor Sao-Ling Chiu
Sao-Ling Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250218922Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.Type: ApplicationFiled: March 17, 2025Publication date: July 3, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Publication number: 20250210461Abstract: A method includes forming a die, which includes forming a first metal pillar on a first side of a first semiconductor substrate of the die, polishing the first semiconductor substrate of the die to reveal a first through-via in the first semiconductor substrate, and forming a second metal pillar on a second side of the die. The first side and the second side are on opposite sides of the first semiconductor substrate. The method further includes encapsulating the die in an encapsulant, forming a first conductive feature on the first side of the first semiconductor substrate and electrically connecting to the first metal pillar, and forming a second conductive feature on the second side of the first semiconductor substrate and electrically connecting to the second metal pillar.Type: ApplicationFiled: March 15, 2024Publication date: June 26, 2025Inventors: Yao-Jen Chang, Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Hsien-Pin Hu, Hao-Yi Tsai, Shang-Yun Hou
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Publication number: 20250149486Abstract: A method includes forming a first conductive pillar on an interposer; forming a second conductive pillar on the interposer, wherein the second conductive pillar includes a barrier layer; bonding a first semiconductor device to the first conductive pillar by a first bonding region that includes more inter-metallic compound than solder; and bonding the first semiconductor device to the second conductive pillar by a second bonding region that includes more solder than inter-metallic compound.Type: ApplicationFiled: February 6, 2024Publication date: May 8, 2025Inventors: Yao-Jen Chang, Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Hsien-Pin Hu
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Patent number: 12283541Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.Type: GrantFiled: January 14, 2024Date of Patent: April 22, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Publication number: 20250069980Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
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Patent number: 12170237Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: GrantFiled: June 14, 2023Date of Patent: December 17, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
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Publication number: 20240371782Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.Type: ApplicationFiled: July 17, 2024Publication date: November 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
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Patent number: 12113027Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.Type: GrantFiled: June 27, 2023Date of Patent: October 8, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
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Publication number: 20240222242Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: ApplicationFiled: March 19, 2024Publication date: July 4, 2024Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20240153861Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.Type: ApplicationFiled: January 14, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11916009Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.Type: GrantFiled: May 30, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Patent number: 11901306Abstract: Semiconductor structures are provided. A semiconductor structure includes a plurality of product regions over a semiconductor substrate, a plurality of alignment regions over the semiconductor substrate, and a plurality of first features formed in a material layer over the semiconductor substrate. Each of the alignment regions is surrounded by four of the product regions of a group, and each of the first features extends across two adjacent product regions in the group. The product regions are disposed in rows and columns of a first array, and the alignment regions are disposed in rows and columns of a second array, and the first and second arrays have a same center point.Type: GrantFiled: November 9, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yu Lu, Yao-Jen Chang, Sao-Ling Chiu
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Patent number: 11810793Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.Type: GrantFiled: July 26, 2022Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
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Publication number: 20230335502Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.Type: ApplicationFiled: June 27, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
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Publication number: 20230326826Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
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Patent number: 11728254Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: May 22, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Patent number: 11728278Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.Type: GrantFiled: September 5, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
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Patent number: 11715675Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.Type: GrantFiled: March 8, 2022Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
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Patent number: 11715681Abstract: A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.Type: GrantFiled: August 30, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Wei Chiu, Sao-Ling Chiu