Abstract: Methods, circuits, apparatus, and systems for managing multi-phase clocking signals for integrated circuit devices are provided. In one aspect, an integrated circuit device includes: a clock signal generator configured to generate a reference clock signal and a plurality of processing units coupled to the clock signal generator. At least one of the plurality of processing units includes: a phase generator configured to selectively generate at least two sets of multi-phase clock signals based on the reference clock signal and corresponding control signals, the at least two sets of multi-phase clock signals having different respective frequencies; and a computation unit configured to perform at least one computing function based on a selected one of the at least two sets of multi-phase clock signals.

Abstract: An electronic system for calculating and mining digital currency using circuit layout optimized for power consumption, performance level, and integrated circuit surface area. A circuit simulation system simulates and evaluates circuit layouts retrieved from a circuit database to identify circuit parameters to compare against threshold values. The circuit simulation varies operational parameters of the circuits simulated to evaluate the active circuit parameters. The operational parameters include voltage levels, clock frequencies, thermal characteristics, and layout characteristics of dedicated components and sub-modules. The active circuit parameters include the effective hash rate, power, performance, and surface area.

Abstract: Dynamically calculating an optimal operational efficiency configuration of a plurality of digital currency mining systems based on trending information related to the digital currency and extrinsic factors affecting the plurality of digital currency mining. The plurality of digital currency mining systems are sent configuration settings to achieve the optimal operational efficiency configuration.

Abstract: A local buffer is integrated with a witness generator and a proof generator on a cryptographic processor and is separate from host memory accessed by a host processor operating with the cryptographic processor in a proving computing system. The witness generator: receives, from software program running on the host processor, compiled code of a zero-knowledge-proof (ZKP) program and specific input to the ZKP program; executes the ZKP program by way of executing the compiled code; records specific output generated from the ZKP program with the specific input, intermediate variable values, and the specific input, as a specific witness of executing the ZKP program; stores the specific witness in the local buffer. The proof generator: receives, from the software program running on the host processor, a proving key; accesses the specific witness in the local buffer; generates a specific zero-knowledge proof for executing the ZKP program with the specific input.

Abstract: The present embodiments provide a solution for clock delivery, distribution to an entire waferscale system composed of many chiplets. A clock distribution scheme according to embodiments is also fault tolerant, i.e., the clock distribution network can avoid faulty chiplets on the substrate and reliably distribute clock to all the functional chiplets which are accessible by the network.

Abstract: A local buffer is integrated with a witness generator and a proof generator on a cryptographic processor and is separate from host memory accessed by a host processor operating with the cryptographic processor in a proving computing system. The witness generator: receives, from software program running on the host processor, compiled code of a zero-knowledge-proof (ZKP) program and specific input to the ZKP program; executes the ZKP program by way of executing the compiled code; records specific output generated from the ZKP program with the specific input, intermediate variable values, and the specific input, as a specific witness of executing the ZKP program; stores the specific witness in the local buffer. The proof generator: receives, from the software program running on the host processor, a proving key; accesses the specific witness in the local buffer; generates a specific zero-knowledge proof for executing the ZKP program with the specific input.

Abstract: A densely integrated and chiplet/dielet based networked memory pool with very high intra-pool bandwidth is provided. Chiplets are used to provide a common interface to the network. This means all memories (even those built with different process technologies) look the same from the network's perspective and vice versa: memory can be assembled in many different configurations while only changing the configuration at a high level of abstraction. The memory pool can easily be scaled in capacity and custom configurations that were previously impossible to achieve because of incompatibility of different technologies or level of integration are made possible.

Abstract: A local buffer is integrated with a witness generator and a proof generator on a cryptographic processor and is separate from host memory accessed by a host processor operating with the cryptographic processor in a proving computing system. The witness generator: receives, from software program running on the host processor, compiled code of a zero-knowledge-proof (ZKP) program and specific input to the ZKP program; executes the ZKP program by way of executing the compiled code; records specific output generated from the ZKP program with the specific input, intermediate variable values, and the specific input, as a specific witness of executing the ZKP program; stores the specific witness in the local buffer. The proof generator: receives, from the software program running on the host processor, a proving key; accesses the specific witness in the local buffer; generates a specific zero-knowledge proof for executing the ZKP program with the specific input.

Abstract: System and methods to train a neural network to systematically find a cross-over point, given the number of devices (e.g., Graphical Processing Units) used to train a deep learning (DL) model, that indicates which parallelization strategy to implement when optimizing the training of the DL model on a particular system to achieve maximum efficiency gains.