Patents by Inventor SAPTARSI DAS

SAPTARSI DAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11915118
    Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: February 27, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Saptarsi Das, Sabitha Kusuma, Sehwan Lee, Ankur Deshwal, Kiran Kolar Chandrasekharan
  • Patent number: 11854174
    Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: December 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dinesh Kumar Yadav, Ankur Deshwal, Saptarsi Das, Junwoo Jang, Sehwan Lee
  • Publication number: 20230186050
    Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Saptarsi DAS, Sabitha KUSUMA, Sehwan LEE, Ankur DESHWAL, Kiran Kolar CHANDRASEKHARAN
  • Patent number: 11604958
    Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Saptarsi Das, Sabitha Kusuma, Sehwan Lee, Ankur Deshwal, Kiran Kolar Chandrasekharan
  • Publication number: 20220374651
    Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.
    Type: Application
    Filed: June 28, 2022
    Publication date: November 24, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: DINESH KUMAR YADAV, ANKUR DESHWAL, SAPTARSI DAS, Junwoo JANG, Sehwan LEE
  • Patent number: 11423251
    Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 23, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dinesh Kumar Yadav, Ankur Deshwal, Saptarsi Das, Junwoo Jang, Sehwan Lee
  • Publication number: 20220036243
    Abstract: An apparatus includes a global memory and a systolic array. The global memory is configured to store and provide an input feature map (IFM) vector stream from an IFM tensor and a kernel vector stream from a kernel tensor. The systolic array is configured to receive the IFM vector stream and the kernel vector stream from the global memory. The systolic array is on-chip together with the global memory. The systolic array includes a plurality of processing elements (PEs) each having a plurality of vector units, each of the plurality of vector units being configured to perform a dot-product operation on at least one IFM vector of the IFM vector stream and at least one kernel vector of the kernel vector stream per unit clock cycle to generate a plurality of output feature maps (OFMs).
    Type: Application
    Filed: January 13, 2021
    Publication date: February 3, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Saptarsi Das, Sabitha Kusuma, Arnab Roy, Ankur Deshwal, Kiran Kolar Chandrasekharan, Sehwan Lee
  • Publication number: 20210150313
    Abstract: A method for computing an inner product on a binary data, a ternary data, a non-binary data, and a non-ternary data using an electronic device. The method includes calculating the inner product on a ternary data, designing a fused bitwise data path to support the inner product calculation on the binary data and the ternary data, designing a FPL data path to calculate an inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data, and distributing the inner product calculation for the binary data and the ternary data and the inner product between one of the non-binary data and the non-ternary data and one of the binary data and the ternary data in the fused bitwise data path and the FPL data path.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 20, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Arnab ROY, Saptarsi DAS, Ankur DESHWAL, Kiran Kolar CHANDRASEK HARAN, Sehwan LEE
  • Publication number: 20200293858
    Abstract: A method and an apparatus for processing layers in a neural network fetch Input Feature Map (IFM) tiles of an IFM tensor and kernel tiles of a kernel tensor, perform a convolutional operation on the IFM tiles and the kernel tiles by exploiting IFM sparsity and kernel sparsity, and generate a plurality of OFM tiles corresponding to the IFM tiles.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 17, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Saptarsi DAS, Sabitha KUSUMA, Sehwan LEE, Ankur DESHWAL, Kiran Kolar CHANDRASEKHARAN
  • Publication number: 20200218936
    Abstract: A method of performing convolution in a neural network with variable dilation rate is provided. The method includes receiving a size of a first kernel and a dilation rate, determining at least one of size of one or more disintegrated kernels based on the size of the first kernel, a baseline architecture of a memory and the dilation rate, determining an address of one or more blocks of an input image based on the dilation rate, and one or more parameters associated with a size of the input image and the memory. Thereafter, the one or more blocks of the input image and the one or more disintegrated kernels are fetched from the memory, and an output image is obtained based on convolution of each of the one or more disintegrated kernels and the one or more blocks of the input image.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 9, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: DINESH KUMAR YADAV, ANKUR DESHWAL, SAPTARSI DAS, Junwoo JANG, Sehwan LEE