Abstract: A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.

Abstract: A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.