Abstract: A system for providing accurately time stamped vehicle operational messages following a real-time clock reset includes a vehicle control computer having a processor, a memory and a real-time clock powered by a constant power source. The processor is operable to store a current value of the real-time clock in memory at engine shut down and to determine whether a clock reset event occurred since the previous engine operational cycle by testing a clock error flag in memory. If such a clock reset event occurred, the processor is operable to reset the real-time clock at the clock value stored at engine shut down and store this value in an error buffer of the memory. Upon establishment of communications with a time correction device having a master real-time clock, the processor is operable to determine whether the error buffer contains any clock values therein.