Patents by Inventor Sarabjit Mehta

Sarabjit Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10345518
    Abstract: A photonic waveguide for conducting light having first and second wavelengths, the waveguide comprising superposed first and second strips of light conducting semiconductor materials having first and second refractive indexes, wherein the second wavelength is shorter than the first wavelength and the second refractive index is higher than the first refractive index, wherein the width and height of the first strip of light conducting semiconductor material are such that the first strip of light conducting semiconductor material is adapted to confine an optical mode of the first wavelength and the width and height of the second strip of light conducting semiconductor material are such that the second strip of light conducting semiconductor material is adapted to confine an optical mode of the second wavelength but is too narrow to confine an optical mode of the first wavelength.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 9, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Troy Rockwood, Kevin Geary, Sarabjit Mehta
  • Patent number: 9726818
    Abstract: A photonic waveguide for conducting light having first and second wavelengths, the waveguide comprising superposed first and second strips of light conducting semiconductor materials having first and second refractive indexes, wherein the second wavelength is shorter than the first wavelength and the second refractive index is higher than the first refractive index, wherein the width and height of the first strip of light conducting semiconductor material are such that the first strip of light conducting semiconductor material is adapted to confine an optical mode of the first wavelength and the width and height of the second strip of light conducting semiconductor material are such that the second strip of light conducting semiconductor material is adapted to confine an optical mode of the second wavelength but is too narrow to confine an optical mode of the first wavelength.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 8, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Troy Rockwood, Kevin Geary, Sarabjit Mehta
  • Patent number: 9660314
    Abstract: A tunable antenna includes a patch antenna including a substrate, a metallic patch mounted on a first side of the substrate, a signal line connected through the substrate to the metallic patch, and a ground plane on a second side of the substrate opposite the first side. The tunable antenna includes an ionizable gas adjacent to the patch antenna.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: May 23, 2017
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta
  • Patent number: 9520525
    Abstract: An infrared photo-detector with multiple discrete regions of a first absorber material. These regions may have geometric shapes with sloped sidewalls. The detector also may include a second absorber region comprising a second absorber material that absorbs light of a shorter wavelength than the light absorbed by the multiple discrete absorber regions of the first absorber material. The geometric shapes may extend only through the first absorber material. Alternatively, the geometric shapes may extend partially into the second absorber region. The detector has a metal reflector coupled to the multiple discrete absorber regions. The detector also has a substrate containing the discrete absorber regions and the second absorber region. The substrate can further include geometric shaped features etched into the substrate, with those features formed on the side of the substrate opposite the side containing the discrete absorber regions and the second absorber region.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: December 13, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Hasan Sharifi
  • Patent number: 8969986
    Abstract: An infrared photo-detector with multiple discrete regions of a first absorber material. These regions may have geometric shapes with sloped sidewalls. The detector also may include a second absorber region comprising a second absorber material that absorbs light of a shorter wavelength than the light absorbed by the multiple discrete absorber regions of the first absorber material. The geometric shapes may extend only through the first absorber material. Alternatively, the geometric shapes may extend partially into the second absorber region. The detector has a metal reflector coupled to the multiple discrete absorber regions. The detector also has a substrate containing the discrete absorber regions and the second absorber region. The substrate can further include geometric shaped features etched into the substrate, with those features formed on the side of the substrate opposite the side containing the discrete absorber regions and the second absorber region.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Hasan Sharifi
  • Patent number: 8946839
    Abstract: An absorber is disclosed. The disclosed absorber contains a base layer, and a plurality of pillars disposed above the base layer and composed of material configured to absorb an incident light and generate minority electrical carriers and majority electrical carrier, wherein the height of the pillars is predetermined to provide a common pyramidal outline shared by the pillars in the plurality of pillars.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, James H. Schaffner
  • Patent number: 7992271
    Abstract: A processes for manufacturing actuating assembly for tuning a circuit by forming a carrier substrate containing a membrane, a conductive layer, and piezoelectric actuators are disclosed.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: August 9, 2011
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta
  • Patent number: 7928389
    Abstract: An apparatus and method for a detector are disclosed. The apparatus disclosed contains an extractor layer, an absorber layer disposed adjacent to the extractor layer, a first electrical contact and a second electrical contact. The absorber layer is configured to absorb photons of incident light and generate minority electrical carriers and majority electrical carriers. In the disclosed apparatus, the top surface of the absorber layer is shaped as a pyramid, the extractor layer is electrically connected with the absorber layer and with the first electrical contact for extracting the minority electrical carriers, and the absorber layer is electrically connected with the extractor layer and with the second electrical contact to extract the majority electrical carriers.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: April 19, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Joseph S. Colburn
  • Patent number: 7868829
    Abstract: A reflectarray is disclosed. The reflectarray includes a first array of conductive patches supported by a substrate, wherein each conductive patch in the first array has a first center line along a Y-direction and a second centerline along an X-direction, a plurality of first variable capacitors, wherein each first variable capacitor is electrically coupled to one of the conductive patches in the first array along the first centerline, and a plurality of second variable capacitors, wherein each second variable capacitor is electrically coupled to one of the conductive patches in the first array along the second centerline.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: January 11, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Joseph S. Colburn, Daniel F. Sievenpiper, Sarabjit Mehta
  • Patent number: 7861398
    Abstract: A method for fabrication of a filter includes forming an input transformer pole in a first substrate by forming a first conductive via, forming an output transformer pole in the first substrate by forming a second conductive via, forming one or more filter poles in the first substrate between the input transformer pole and the output transformer pole by forming one or more conductive vias in the first substrate between the input transformer pole and the output transformer pole, fabricating one or more tuning elements on a second substrate, wherein the number of tuning elements corresponds to the number of filter poles between the input transformer pole and the output transformer pole, and bonding the second substrate to a top surface of the first substrate so that each tuning element on the second substrate is aligned with and overlays a filter pole on the first substrate.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: January 4, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Sarabjit Mehta, Peter Petre
  • Publication number: 20100064493
    Abstract: An actuating assembly for tuning a circuit and a process for forming a carrier substrate containing a membrane, a conductive layer, and piezoelectric actuators are disclosed. The actuating assembly comprises a membrane overlying a circuit to be tuned, a conductive element connected with the membrane, and a piezoelectric arrangement. Changes in shape of the piezoelectric arrangement allow a deflection of the membrane and a corresponding controllable upward or downward movement of the conductive element. In the process, a membrane and a piezoelectric structure are formed on a substrate.
    Type: Application
    Filed: November 20, 2009
    Publication date: March 18, 2010
    Applicant: HRL LABORATORIES, LLC
    Inventor: Sarabjit MEHTA
  • Patent number: 7656071
    Abstract: An actuating assembly for tuning a circuit and a process for forming a carrier substrate containing a membrane, a conductive layer, and piezoelectric actuators are disclosed. The actuating assembly comprises a membrane overlying a circuit to be tuned, a conductive element connected with the membrane, and a piezoelectric arrangement. Changes in shape of the piezoelectric arrangement allow a deflection of the membrane and a corresponding controllable upward or downward movement of the conductive element. In the process, a membrane and a piezoelectric structure are formed on a substrate.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: February 2, 2010
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta
  • Patent number: 7514759
    Abstract: A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: April 7, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Sarabjit Mehta, David E. Grider, Wah S. Wong
  • Patent number: 7405637
    Abstract: A miniature tunable filter comprising filter poles disposed with a filter substrate. A moveable electrically conductive membrane is disposed above each filter pole and is spaced from the filter pole by an air or vacuum gap. The gap spacing is changed by deflecting the membrane with an electrostatic voltage. The change in gap spacing varies the capacitive loading at the pole, thus providing tuning of the filter. The electrically conductive membrane is preferably manufactured on a separate substrate that is bonded to the filter body containing the filter substrate.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: July 29, 2008
    Assignee: HRL Laboratories, LLC
    Inventors: Sarabjit Mehta, Peter Petre
  • Patent number: 7400488
    Abstract: A device for varying the capacitance of an electronic circuit is disclosed. The device comprises a flexible membrane located above the electronic circuit, a metal layer connected to the flexible membrane, and bias circuitry located above the membrane. Variation of the capacitance of the electronic circuit is obtained by pulling the membrane upwards by means of the bias circuitry. The disclosed device provides a sizeable capacitance variation and high Q factor, resulting in overall low filter insertion loss. A nearly constant group delay over a wide operating bandwidth is also obtained.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: July 15, 2008
    Assignee: HRL Laboratories, LLC
    Inventors: Jonathan J. Lynch, Sarabjit Mehta, John Pasiecznik, Peter Petre
  • Patent number: 7343655
    Abstract: A method of fabricating a micro electromechanical switch on a substrate comprising piezoelectric layers, metal electrodes alternated with the layers and contact pads. Cross voltages are applied to the electrodes, in order to obtain an S-shaped deformation of the switch and allow contact between the contact pads. Additionally, a further electrode can be provided on a substrate where the switch is fabricated, to allow an additional electrostatic effect during movement of the piezoelectric layers to obtain contact between the contact pads. The overall dimensions of the switch are very small and the required actuation voltage is very low, when compared to existing switches.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: March 18, 2008
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta
  • Patent number: 7215064
    Abstract: A piezoelectric switch for tunable electronic components comprises piezoelectric layers, metal electrodes alternated with the layers and contact pads. Cross voltages are applied to the electrodes, in order to obtain an S-shaped deformation of the switch and allow contact between the contact pads. Additionally, a further electrode can be provided on a substrate where the switch is fabricated, to allow an additional electrostatic effect during movement of the piezoelectric layers to obtain contact between the contact pads. The overall dimensions of the switch are very small and the required actuation voltage is very low, when compared to existing switches.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: May 8, 2007
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta
  • Publication number: 20070070576
    Abstract: A device for varying the capacitance of an electronic circuit is disclosed. The device comprises a flexible membrane located above the electronic circuit, a metal layer connected to the flexible membrane, and bias circuitry located above the membrane. Variation of the capacitance of the electronic circuit is obtained by pulling the membrane upwards by means of the bias circuitry. The disclosed device provides a sizeable capacitance variation and high Q factor, resulting in overall low filter insertion loss. A nearly constant group delay over a wide operating bandwidth is also obtained.
    Type: Application
    Filed: November 30, 2006
    Publication date: March 29, 2007
    Inventors: Jonathan Lynch, Sarabjit Mehta, John Pasiecznik, Peter Petre
  • Patent number: 7161791
    Abstract: A device for varying the capacitance of an electronic circuit is disclosed. The device comprises a flexible membrane located above the electronic circuit, a metal layer connected to the flexible membrane, and bias circuitry located above the membrane. Variation of the capacitance of the electronic circuit is obtained by pulling the membrane upwards by means of the bias circuitry. The disclosed device provides a sizeable capacitance variation and high Q factor, resulting in overall low filter insertion loss. A nearly constant group delay over a wide operating bandwidth is also obtained.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: January 9, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Jonathan J. Lynch, Sarabjit Mehta, John Pasiecznik, Peter Petre
  • Patent number: 7128843
    Abstract: A process for fabricating monolithic membrane structures having air gaps is disclosed, comprising the steps of: providing a wafer; depositing and patterning a protective layer on the wafer; providing a trench in the wafer; depositing and patterning a metal in the trench; depositing and patterning a sacrificial layer on the metal; depositing and patterning a membrane pad on the sacrificial layer; providing a polymeric film on the protective layer and sacrificial layer, wherein part of the polymeric film has a tensile stress; and releasing part of the polymeric film from the protective layer and sacrificial layer, wherein the tensile stress of a portion of the polymeric film releases the portion of the polymeric film from the wafer and generates the air gap.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 31, 2006
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta