Patents by Inventor Sarad Bahadur Thapa

Sarad Bahadur Thapa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11869942
    Abstract: A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness; an AlN nucleation layer; a first strain building layer which is an AlzGal-zN layer having a first average Al content z, wherein 0<z; a first strain preserving block comprising ?5 and ?50 units of a first sequence of layers, the first sequence comprising an AlN layer and at least two AlGaN layers, and having a second average Al content y, wherein y a second strain building layer which is an AlxGal-xN layer having a third average Al content x, wherein 0?x<y; a second strain preserving block comprising ?5 and ?50 units of a second sequence of layers, the sequence comprising an AlN layer and at least one AlGaN layer, and having a fourth average Al content w, wherein x<w<y, and a GaN layer, wherein the layers between the AlN nucleation layer and the GaN layer form an AlGaN buffer.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: January 9, 2024
    Assignee: SILTRONIC AG
    Inventors: Sarad Bahadur Thapa, Martin Vorderwestner
  • Publication number: 20200203485
    Abstract: A heteroepitaxial wafer comprises, in the following order: a silicon substrate having a diameter and a thickness; an AlN nucleation layer; a first strain building layer which is an AlzGal-zN layer having a first average Al content z, wherein 0<z; a first strain preserving block comprising ?5 and ?50 units of a first sequence of layers, the first sequence comprising an AlN layer and at least two AlGaN layers, and having a second average Al content y, wherein y a second strain building layer which is an AlxGal-xN layer having a third average Al content x, wherein 0?x<y; a second strain preserving block comprising ?5 and ?50 units of a second sequence of layers, the sequence comprising an AlN layer and at least one AlGaN layer, and having a fourth average Al content w, wherein x<w<y, and a GaN layer, wherein the layers between the AlN nucleation layer and the GaN layer form an AlGaN buffer.
    Type: Application
    Filed: August 16, 2018
    Publication date: June 25, 2020
    Applicant: SILTRONIC AG
    Inventors: Sarad Bahadur THAPA, Martin VORDERWESTNER
  • Patent number: 10283356
    Abstract: Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: May 7, 2019
    Assignee: SILTRONIC AG
    Inventors: Sarad Bahadur Thapa, Maik Haeberlen, Marvin Zoellner, Thomas Schroeder
  • Patent number: 10192739
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 29, 2019
    Assignee: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber
  • Patent number: 9923050
    Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<×<1.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 20, 2018
    Assignees: SILTRONIC AG, IMEC VZW
    Inventors: Sarad Bahadur Thapa, Ming Zhao, Peter Storck, Norbert Werner
  • Publication number: 20170372888
    Abstract: Problems associated with the mismatch between a silicon substrate and a group-IIIA nitride layer are addressed by employing a silicon substrate processed to have a surface comprising closely spaced tips extending from the surface, depositing a group-IIIB silicide layer on the tips, then depositing a group-IIIB nitride layer, and then depositing a group-IIIA nitride.
    Type: Application
    Filed: January 15, 2016
    Publication date: December 28, 2017
    Applicant: Siltronic AG
    Inventors: Sarad Bahadur THAPA, Maik HAEBERLEN, Marvin ZOELLNER, Thomas SCHROEDER
  • Publication number: 20160233293
    Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<x<1.
    Type: Application
    Filed: September 11, 2014
    Publication date: August 11, 2016
    Inventors: Sarad Bahadur THAPA, Ming ZHAO, Peter STORCK, Norbert WERNER
  • Patent number: 9147726
    Abstract: A semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) consisting predominantly of silicon and having a (111) surface orientation, a monocrystalline layer (3) of Sc2O3 having a (111) surface orientation, a monocrystalline layer (4) of ScN having a (111) surface orientation, and a monocrystalline layer (6) of AlzGa1-zN with 0?z?1 having a (0001) surface orientation, the semiconductor wafers are produced by appropriate deposition of the respective layers.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: September 29, 2015
    Assignee: Siltronic AG
    Inventors: Sarad Bahadur Thapa, Thomas Schroeder, Lidia Tarnawska
  • Publication number: 20140264776
    Abstract: A semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) consisting predominantly of silicon and having a (111) surface orientation, a monocrystalline layer (3) of Sc2O3 having a (111) surface orientation, a monocrystalline layer (4) of ScN having a (111) surface orientation, and a monocrystalline layer (6) of AlzGa1-zN with 0?z?1 having a (0001) surface orientation, the semiconductor wafers are produced by appropriate deposition of the respective layers.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 18, 2014
    Applicant: Siltronic AG
    Inventors: Sarad Bahadur Thapa, Thomas Schroeder, Lidia Tarnawska
  • Publication number: 20140048848
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Application
    Filed: May 23, 2012
    Publication date: February 20, 2014
    Applicant: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber