Patents by Inventor Sarah A. McTaggart

Sarah A. McTaggart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120144
    Abstract: The disclosure provides bipolar transistor structures with a cavity below an extrinsic base, and methods to form the same. A structure of the disclosure provides a bipolar transistor structure including an extrinsic base protruding from an intrinsic base of a bipolar transistor. The extrinsic base extends over a cavity. An insulator is horizontally adjacent the cavity and below a portion of the extrinsic base. A collector extension region of the bipolar transistor structure extends laterally below the insulator and the cavity.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Uppili S. Raghunathan, Alexander M. Derrickson, Sarah A. McTaggart, Judson Robert Holt, Vibhor Jain
  • Publication number: 20240178290
    Abstract: An integrated circuit (IC) structure includes a V-shaped cavity in a semiconductor substrate. A source region and a drain region are on opposing sides of the V-shaped cavity. A gate structure includes a gate dielectric layer, spacers, and a gate electrode on the gate dielectric layer between the spacers. The gate structure is fully within the V-shaped cavity. The IC structure provides a switch that finds advantageous application as part of a low noise amplifier. The IC structure provides a smaller gate width, decreased capacitance, increased gain and increased radio frequency (RF) performance compared to planar devices or devices without the gate structure fully within V-shaped cavity.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Megan Lydon-Nuhfer, Steven M. Shank, Aaron L. Vallett, Michel Abou-Khalil, Sarah A. McTaggart, Rajendran Krishnasamy
  • Patent number: 11869941
    Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: January 9, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Sarah A. McTaggart, Rajendran Krishnasamy, Qizhi Liu
  • Publication number: 20230352570
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar junction transistor and methods of manufacture. The structure includes: a collector region; a base region adjacent to the collector region; an emitter region adjacent to the base region; contacts having a first material connecting to the collector region and the base region; and at least one contact having a second material connecting to the emitter region.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Inventors: Mark D. Levy, Sarah A. McTaggart, Laura J. Silverstein, Qizhi Liu, Jason E. Stephens
  • Publication number: 20230268394
    Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Applicant: GlobalFoundries U.S. Inc.
    Inventors: Sarah A. McTaggart, Rajendran Krishnasamy, Qizhi Liu
  • Patent number: 9577023
    Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edward C. Cooney, III, Dinh Dang, David A. DeMuynck, Sarah A. McTaggart, Gary L. Milo, Melissa J. Roma, Jeffrey L. Thompson, Thomas W. Weeks
  • Publication number: 20140354392
    Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.
    Type: Application
    Filed: June 4, 2013
    Publication date: December 4, 2014
    Inventors: Edward C. Cooney, III, Dinh Dang, David A. DeMuynck, Sarah A. McTaggart, Gary L. Milo, Melissa J. Roma, Jeffrey L. Thompson, Thomas W. Weeks