Patents by Inventor Sarah A. McTaggart
Sarah A. McTaggart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088157Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Michel Abou-Khalil, Steven M. Shank, Sarah McTaggart, Aaron Vallett, Rajendran Krishnasamy, Megan Lydon-Nuhfer
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Patent number: 11869941Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.Type: GrantFiled: February 24, 2022Date of Patent: January 9, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Sarah A. McTaggart, Rajendran Krishnasamy, Qizhi Liu
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Publication number: 20230352570Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar junction transistor and methods of manufacture. The structure includes: a collector region; a base region adjacent to the collector region; an emitter region adjacent to the base region; contacts having a first material connecting to the collector region and the base region; and at least one contact having a second material connecting to the emitter region.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Inventors: Mark D. Levy, Sarah A. McTaggart, Laura J. Silverstein, Qizhi Liu, Jason E. Stephens
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Publication number: 20230317776Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Michel Abou-Khalil, Steven M. Shank, Aaron Vallett, Sarah McTaggart, Rajendran Krishnasamy
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Publication number: 20230268394Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Applicant: GlobalFoundries U.S. Inc.Inventors: Sarah A. McTaggart, Rajendran Krishnasamy, Qizhi Liu
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Publication number: 20220190145Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Inventors: Sarah McTaggart, Qizhi Liu, Vibhor Jain, Mark Levy, Paula Fisher, James R. Elliott
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Patent number: 11362201Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.Type: GrantFiled: December 14, 2020Date of Patent: June 14, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Sarah McTaggart, Qizhi Liu, Vibhor Jain, Mark Levy, Paula Fisher, James R. Elliott
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Heterojunction bipolar transistors with multiple emitter fingers and undercut extrinsic base regions
Patent number: 10312356Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are arranged to surround a plurality of active regions, and a collector is located in each of the active regions. A base layer includes a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions. The first sections of the base layer contain single-crystal semiconductor material, and the second sections of the base layer contain polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a plurality of cavities. A plurality of emitter fingers are respectively arranged on the first sections of the base layer.Type: GrantFiled: June 20, 2018Date of Patent: June 4, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Qizhi Liu, Vibhor Jain, James W. Adkisson, Sarah McTaggart, Mark Levy -
Patent number: 9577023Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.Type: GrantFiled: June 4, 2013Date of Patent: February 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Edward C. Cooney, III, Dinh Dang, David A. DeMuynck, Sarah A. McTaggart, Gary L. Milo, Melissa J. Roma, Jeffrey L. Thompson, Thomas W. Weeks
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Publication number: 20140354392Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.Type: ApplicationFiled: June 4, 2013Publication date: December 4, 2014Inventors: Edward C. Cooney, III, Dinh Dang, David A. DeMuynck, Sarah A. McTaggart, Gary L. Milo, Melissa J. Roma, Jeffrey L. Thompson, Thomas W. Weeks