Patents by Inventor Sarah C. Prue

Sarah C. Prue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Content based yield prediction of VLSI designs
    Patent number: 7661081
    Abstract: An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Daria R. Dooling, Jason D. Hibbeler, Daniel N. Maynard, Sarah C. Prue, Ralph J. Williams
  • CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
    Publication number: 20080195989
    Abstract: An integrated circuit and program product for predicting yield of a VLSI design. An integrated circuit is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.
    Type: Application
    Filed: April 11, 2008
    Publication date: August 14, 2008
    Inventors: Robert J. Allen, Daria R. Dooling, Jason D. Hibbeler, Daniel N. Maynard, Sarah C. Prue, Ralph J. Williams
  • Content based yield prediction of VLSI designs
    Patent number: 7389480
    Abstract: A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within the integrated circuit design; and applying different yield models to critical area values based on the types of the regions used to calculate the critical area values, wherein each yield model is dependent on a type.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Daria R. Dooling, Jason D. Hibbeler, Daniel N. Maynard, Sarah C. Prue, Ralph J. Williams
  • Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing
    Patent number: 7240306
    Abstract: Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: July 3, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Peter K. Chan, Evanthia Papadopoulou, Sarah C. Prue, Mervyn Y. Tan