Patents by Inventor Sarah H. Knickerbocker
Sarah H. Knickerbocker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079360Abstract: A bonding structure for a semiconductor substrate and related method are provided. The bonding structure includes a first oxide layer on the semiconductor substrate, and a second oxide layer on the first oxide layer, the second oxide layer for bonding to another structure. The second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer. The second oxide layer may also have a higher density than the first oxide layer. The bonding structure can be used to bond chips to wafer or wafer to wafer and provides a greater bond strength than just a thick oxide layer.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Jorge A. Lubguban, Sarah H. Knickerbocker, Lloyd Burrell, John J. Garant, Matthew C. Gorfien
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Publication number: 20210173145Abstract: Photonic integrated circuit (PIC) packages include a PIC die. The PIC die includes a waveguide(s) positioned on the PIC die, and a groove(s) formed in a surface of the PIC die. The groove(s) corresponds to and is positioned directly adjacent the waveguide(s). The PIC package also includes an optical fiber(s) operatively coupled to the waveguide(s) of the PIC die. The optical fiber(s) are positioned in the groove(s) of the PIC die and include an end positioned adjacent the waveguide(s). Additionally, the PIC package includes a plate positioned over a section of the optical fiber(s), and the plate includes a first edge positioned adjacent the waveguide(s) of the PIC die, and a second edge positioned opposite the first edge. The PIC package also includes a first adhesive disposed along the second edge of the plate and a second adhesive disposed along the first edge of the plate.Type: ApplicationFiled: December 4, 2019Publication date: June 10, 2021Inventors: Benjamin V. Fasano, Jorge A. Lubguban, Sarah H. Knickerbocker, Tracy A. Tong
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Patent number: 10090255Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.Type: GrantFiled: January 29, 2016Date of Patent: October 2, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Brittany L. Hedrick, Vijay Sukumaran, Christopher L. Tessler, Richard F. Indyk, Sarah H. Knickerbocker
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Publication number: 20170221837Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.Type: ApplicationFiled: January 29, 2016Publication date: August 3, 2017Inventors: Brittany L. Hedrick, Vijay Sukumaran, Christopher L. Tessler, Richard F. Indyk, Sarah H. Knickerbocker
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Patent number: 9401336Abstract: A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.Type: GrantFiled: November 4, 2014Date of Patent: July 26, 2016Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Sarah H. Knickerbocker, Karen P. McLaughlin, David J. Russell
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Patent number: 9362223Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: GrantFiled: August 18, 2015Date of Patent: June 7, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, HITACHI CHEMICIAL DUPONT MICROSYSTEMS, L.L.C.Inventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Publication number: 20160126201Abstract: A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.Type: ApplicationFiled: November 4, 2014Publication date: May 5, 2016Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Sarah H. Knickerbocker, Karen P. McLaughlin, David J. Russell
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Publication number: 20150357283Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Patent number: 9209128Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: GrantFiled: April 1, 2014Date of Patent: December 8, 2015Assignees: International Business Machines Corporation, HITACHI CHEMICAL DUPONT MICROSYSTEMS, L.L.C.Inventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Patent number: 9171749Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.Type: GrantFiled: November 13, 2013Date of Patent: October 27, 2015Assignee: GLOBALFOUNDRIES U.S.2 LLCInventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, Jr., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
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Publication number: 20150279779Abstract: A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.Type: ApplicationFiled: April 1, 2014Publication date: October 1, 2015Applicants: Hitachi Chemical DuPont Microsystems, L.L.C., International Business Machines CorporationInventors: Paul S. Andry, Sarah H. Knickerbocker, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman
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Publication number: 20150132924Abstract: A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.Type: ApplicationFiled: November 13, 2013Publication date: May 14, 2015Applicant: International Business Machines CorporationInventors: Bing Dang, Sarah H. Knickerbocker, Douglas C. La Tulipe, JR., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel
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Patent number: 8807184Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.Type: GrantFiled: February 22, 2013Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Sarah H. Knickerbocker, Jonathan H. Griffith
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Publication number: 20140192341Abstract: Methods for determining the planarity of two components of a semiconductor processing tool, such as a 3D wafer bonder are disclosed. The two components may be fixtures, chucks, or platens of the tool. A test wafer comprising multiple solder balls is compressed and the deformity of multiple solder balls is measured to assess the planarity of the tool. The measurement of the deformed solder balls may be performed manually, or with an automated wafer inspection tool, which may use lasers to measure the height of each solder ball. The planarity of the two components is computed based on the height of the deformed solder balls.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sarah H. Knickerbocker, Jerry Allen Gorrell, Christopher Lee Tessler
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Patent number: 8753460Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.Type: GrantFiled: January 28, 2011Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Sarah H. Knickerbocker, Jonathan H. Griffith
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Patent number: 8668834Abstract: A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.Type: GrantFiled: April 23, 2012Date of Patent: March 11, 2014Assignee: International Business Machines CorporationsInventors: Bradley P. Jones, Sarah H. Knickerbocker, Richard P. Volant
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Publication number: 20120207920Abstract: A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.Type: ApplicationFiled: April 23, 2012Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradley P. Jones, Sarah H. Knickerbocker, Richard P. Volant
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Publication number: 20120193014Abstract: Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.Type: ApplicationFiled: January 28, 2011Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: SARAH H. KNICKERBOCKER, Jonathan H. Griffith
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Patent number: 7999377Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.Type: GrantFiled: February 11, 2008Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Edward M. DeMulder, Sarah H. Knickerbocker, Michael J. Shapiro, Albert M. Young
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Publication number: 20110079702Abstract: A method of forming a mold having a protective layer includes forming a mold substrate having at least one substantially planar surface, depositing a layer of mold protection material onto the at least one substantially planar surface, and etching a plurality of cavities into the at least one substantially planar surface through the mold protection layer.Type: ApplicationFiled: October 6, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bradley P. Jones, Sarah H. Knickerbocker, Richard P. Volant