Patents by Inventor Sarah J. Lane

Sarah J. Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7291280
    Abstract: The present invention provides a method for polishing silica and silicon nitride on a semiconductor wafer comprising the steps of planarizing the silica with a first aqueous composition comprising by weight percent 0.01 to 5 carboxylic acid polymer, 0.02 to 6 abrasive, 0.01 to 10 polyvinylpyrrolidone, 0 to 5 cationic compound, 0 to 1 phthalic acid and salts, 0 to 5 zwitterionic compound and balance water, wherein the polyvinylpyrrolidone has an average molecular weight between 100 grams/mole to 1,000,000 grams/mole. The method further provides detecting an endpoint to the planarization, and clearing the silica with a second aqueous composition comprising by weight percent 0.001 to 1 quaternary ammonium compound, 0.001 to 1 phthalic acid and salts thereof, 0.01 to 5 carboxylic acid polymer, 0.01 to 5 abrasive and balance water.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: November 6, 2007
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Sarah J. Lane, Andrew Scott Lawing, Brian L. Mueller, Charles Yu
  • Patent number: 4732629
    Abstract: This invention provides a method of increasing the cut-through resistance of a PTFE insulated conductor. Unsintered PTFE is expanded and compressed and then applied to a conductor. The insulated conductor is then heated to a temperature above 345.degree. C. The compressed, expanded PTFE has one crystalline melt point above 375.degree. C.
    Type: Grant
    Filed: July 25, 1986
    Date of Patent: March 22, 1988
    Inventors: Peter B. Cooper, Sarah J. Lane