Patents by Inventor Sarah Knickerbocker
Sarah Knickerbocker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10520679Abstract: An optical system includes a photonics chip, a bridge waveguide structure formed on the chip, and an optical fiber disposed over the chip and optically aligned with the bridge waveguide structure. A cavity between the bridge waveguide structure and the chip is at least partially filled with an adhesive resin and a filler material having a coefficient of thermal expansion (CTE) less than that of the adhesive resin. The filler material may include filler particles dispersed throughout the adhesive resin, or a discrete layer of material separate from the adhesive resin. The composite adhesive material filling the cavity has an effective coefficient of thermal expansion less than the coefficient of thermal expansion of conventional adhesive resins. This lower effective CTE improves the survivability of the overlying bridge waveguide structure following thermal cycling of the optical system.Type: GrantFiled: June 5, 2018Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Sarah Knickerbocker, Jorge Lubguban, Tracy Tong
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Publication number: 20190369339Abstract: An optical system includes a photonics chip, a bridge waveguide structure formed on the chip, and an optical fiber disposed over the chip and optically aligned with the bridge waveguide structure. A cavity between the bridge waveguide structure and the chip is at least partially filled with an adhesive resin and a filler material having a coefficient of thermal expansion (CTE) less than that of the adhesive resin. The filler material may include filler particles dispersed throughout the adhesive resin, or a discrete layer of material separate from the adhesive resin. The composite adhesive material filling the cavity has an effective coefficient of thermal expansion less than the coefficient of thermal expansion of conventional adhesive resins. This lower effective CTE improves the survivability of the overlying bridge waveguide structure following thermal cycling of the optical system.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Sarah Knickerbocker, Jorge Lubguban, Tracy Tong
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Publication number: 20070080448Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward DeMulder, Sarah Knickerbocker, Michael Shapiro, Albert Young
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Publication number: 20060249854Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.Type: ApplicationFiled: June 29, 2006Publication date: November 9, 2006Inventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Samuel McKnight, Kevin Petrarca, Kamalesh Srivastava, Roger Quon
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Publication number: 20060081981Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: November 10, 2005Publication date: April 20, 2006Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Publication number: 20060009022Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: ApplicationFiled: September 12, 2005Publication date: January 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamalesh Srivastava, Subhash Shinde, Tien-Jen Cheng, Sarah Knickerbocker, Roger Quon, William Sablinski, Julie Biggs, David Eichstadt, Jonathan Griffith
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Publication number: 20050208748Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamalesh Srivastava, Subhash Shinde, Tien-Jen Cheng, Sarah Knickerbocker, Roger Quon, William Sablinski, Julie Biggs, David Eichstadt, Jonathan Griffith
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Publication number: 20050167837Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.Type: ApplicationFiled: January 21, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Samuel McKnight, Kevin Petrarca, Kamalesh Srivastava, Roger Quon
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Publication number: 20050103636Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.Type: ApplicationFiled: November 18, 2003Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Rosemary Previti-Kelly, Roger Quon, Kamalesh Srivastava, Keith Wong
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Publication number: 20050062170Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Patent number: 6284574Abstract: A structure and process are described for facilitating the conduction of heat away from a semiconductor device. Thermally conductive planes and columns are incorporated within the back-end structure and around the interconnect outside the chip. A thermally conductive plane is formed by forming a first insulating layer on an underlying layer of the device; forming a recess in the insulating layer; filling the recess with a thermally conductive material to form a lateral heat-dissipating layer; planarizing the heat-dissipating layer to make the top surface thereof coplanar with the unrecessed portion of the insulating layer; and forming a second insulating layer on the first insulating layer and the heat-dissipating layer, thereby embedding the heat-dissipating layer between the first and second insulating layers. The heat-dissipating layer is electrically isolated from the underlying layer of the device, and preferably is electrically grounded.Type: GrantFiled: January 4, 1999Date of Patent: September 4, 2001Assignee: International Business Machines CorporationInventors: Kevin Shawn Petrarca, Sarah Knickerbocker, Joyce C. Liu, Rebecca D. Mih