Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.

Abstract: A serial data link measurement and simulation system for use on a test and measurement instrument presents on a display device. A main menu having elements representing a measurement circuit, a simulation circuit and a transmitter. The main menu includes processing flow lines pointing from the measurement circuit to the transmitter and from the transmitter to the simulation circuit. The main menu includes a source input to the measurement circuit and one or more test points from which waveforms may be obtained. The simulation circuit includes a receiver. The measurement and simulation circuits are defined by a user, and the transmitter is common to both circuits so all aspects of the serial data link system are tied together.

Abstract: A serial data link measurement and simulation system for use on a test and measurement instrument presents on a display device a main menu having elements representing a measurement circuit, a simulation circuit and a transmitter. The main menu includes processing flow lines pointing from the measurement circuit to the transmitter and from the transmitter to the simulation circuit. The main menu includes a source input to the measurement circuit and one or more test points from which waveforms may be obtained. The simulation circuit includes a receiver. The measurement and simulation circuits are defined by a user, and the transmitter is common to both circuits so all aspects of the serial data link system are tied together.