Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract: A stream of bits are received in a first integrated circuit (IC) device, where the stream represents a sequence of symbols transmitted by a second IC device over a serial point to point link that couples the two devices. First and second M-bit sections of the stream are compared to a non-data symbol. The second M-bit section is offset by one bit in the stream relative to the first section. If there is a match between the first section and the non-data symbol, then a flag indicating symbol alignment is asserted. Each of multiple, consecutive, non overlapping M-bit sections that follow the first section are then to be treated as separate symbols. Other embodiments are also described and claimed.

Abstract: An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the link. Digitally-controllable transmission line terminations are provided for the driver and receiver circuits, respectively. A digitally-controllable reference signal level is also provided for the I/O buffer. A number of impedance matching compensation values are automatically calibrated against one or more reference resistors, by calibrating a first value and then a second value, and a third value. These calibrated values are automatically applied to set the reference signal level, driver termination, and receiver termination, respectively. Other embodiments are also described and claimed.

Abstract: According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.

Abstract: According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.

Abstract: A method and apparatus for open loop buffer allocation. In one embodiment, the method includes loading requested data within a buffer according to a load rate. Concurrent with the loading of data within the buffer, the data is forwarded from the buffer according to drain rate. In situations where the load rate exceeds the drain rate, read requests may be throttled according to an approximate buffer capacity level to prohibit buffer overflow. In one embodiment, a rate for issuing data requests, for example, to memory, is regulated according to a predetermined buffer accumulation rate. Accordingly, in one embodiment, the open loop allocation scheme reduces latency while enabling sustained read streaming with a minimal size read buffer. Other embodiments are described and claimed.

Abstract: A stream of bits are received in a first integrated circuit (IC) device, where the stream represents a sequence of symbols transmitted by a second IC device over a serial point to point link that couples the two devices. First and second M-bit sections of the stream are compared to a non-data symbol. The second M-bit section is offset by one bit in the stream relative to the first section. If there is a match between the first section and the non-data symbol, then a flag indicating symbol alignment is asserted. Each of multiple, consecutive, non overlapping M-bit sections that follow the first section are then to be treated as separate symbols. Other embodiments are also described and claimed.

Abstract: A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.

Abstract: A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.

Abstract: An integrated circuit (IC) device that has an analog front end with an I/O buffer is reset. The I/O buffer has a driver circuit to transmit a stream of information over a serial point to point link, and a receiver circuit to receive a stream of information over the link. Digitally-controllable transmission line terminations are provided for the driver and receiver circuits, respectively. A digitally-controllable reference signal level is also provided for the I/O buffer. A number of impedance matching compensation values are automatically calibrated against one or more reference resistors, by calibrating a first value and then a second value, and a third value. These calibrated values are automatically applied to set the reference signal level, driver termination, and receiver termination, respectively. Other embodiments are also described and claimed.

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.