Patents by Inventor Sarath Kumar Jha

Sarath Kumar Jha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10355818
    Abstract: The present embodiments relate to methods and apparatuses for detecting a codeword boundary and/or performing codeword error correction for a bitstream comprising scrambled Reed Solomon codewords. In accordance with some aspects, detecting a codeword boundary involves the use of the parity and symbols from a previous window to help in detecting a codeword boundary when the next input bit is received. In accordance with other aspects, parity symbols are more efficiently updated for each successive candidate input bit. In accordance with still further aspects, error correction during codeword boundary detection can be either partially performed or completely bypassed.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 16, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Sarath Kumar Jha
  • Patent number: 10020824
    Abstract: An improved approach is provided to identifying the boundary of data encoded using additive cyclic codes. In some embodiment, the process includes determining a first calculated parity of a first bit stream window, and, second, one or more updates to the calculated parity of the bit stream window to determine the parity of the next bit stream window, where after each update to the calculated parity, the calculated parity is compared with the target parity, and matching the calculated parity to the target parity indicates a proper boundary of a bit stream window. In some embodiments, the process supports shortened cyclic codes. In some embodiments, the bit stream boundary can be identified prior to descrambling the bit stream inputs for a given bit stream window. In this way, the process can avoid unnecessarily descrambling of the bit stream windows that are not properly aligned to a bit stream boundary.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: July 10, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sarath Kumar Jha
  • Patent number: 9882585
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method of improving a speed of decoding digital data. The method may include receiving a digital communication that includes digital data; specifying a partition of a plurality of elements of a Galois field into a plurality of sets; specifying an error locator polynomial function for a Reed-Solomon forward error correction module; specifying, for each set of the plurality of sets, a second function dependent upon the error locator polynomial function and one or more characteristics of the respective set; computing the second function for each of the plurality of sets to find roots of the error locator polynomial function; outputting the roots of the error locator polynomial function to a Reed-Solomon forward error correction decoder module; and decoding the digital data included in the received digital communication using the roots.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: January 30, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sarath Kumar Jha