Abstract: An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Abstract: A Peripheral Component Interconnect express (PCIe) device may include at least one Direct Memory Access (DMA) device and a PCIe controller. The PCIe controller may count, in units of data blocks each having a predetermined size, an amount of data about target commands respectively allocated to multi-functions executed in the at least one DMA device, and determine, among the multi-functions, candidate functions to receive new commands from a host based on a result obtained by comparing the counted amount for each of the multi-functions with a threshold value.

Abstract: A storage device for outputting a program completion response before a program operation is completed includes a buffer memory for storing data from a host, a memory device for storing data from the buffer memory, and a memory controller for controlling the buffer memory and the memory device. The buffer memory stores the data according to mapping information. The memory controller includes a response controller for outputting a remapping request for changing mapping in the buffer memory, when the data and a storage request corresponding thereto are received, and outputting a storage completion response, when a remapping operation is completed, and a mapping controller for outputting, based on the remapping request, the mapping information on usable storage areas except an unusable area, by performing a remapping operation of changing an area in which the data is stored among the usable storage areas of the buffer memory to the unusable area.

Abstract: An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Abstract: A storage device for outputting a program completion response before a program operation is completed includes a buffer memory for storing data from a host, a memory device for storing data from the buffer memory, and a memory controller for controlling the buffer memory and the memory device. The buffer memory stores the data according to mapping information. The memory controller includes a response controller for outputting a remapping request for changing mapping in the buffer memory, when the data and a storage request corresponding thereto are received, and outputting a storage completion response, when a remapping operation is completed, and a mapping controller for outputting, based on the remapping request, the mapping information on usable storage areas except an unusable area, by performing a remapping operation of changing an area in which the data is stored among the usable storage areas of the buffer memory to the unusable area.

Abstract: Provided are method for dynamically allocating resources to command queues and response queues by a non-volatile memory (NVM) controller. The method includes creating command queues and response queues for at least one operating system among a plurality of operating systems running on a host system and mapping the created command queues and response queues to a plurality of internal shared queue registers. The plurality of operating systems running on the host system communicate with at least one NVM controller independently.

Abstract: An interrupt generation method of a storage device includes executing a command provided by a host, writing a completion entry in a completion queue of the host upon completing execution of the command, and issuing an interrupt corresponding to the completion entry to the host in response to at least one of a first interrupt generation condition, a second interrupt generation condition, and a third interrupt generation condition being satisfied. The first interrupt generation condition is satisfied when a difference between a tail pointer and a head pointer of the completion queue is equal to a first mismatch value. The second interrupt generation condition is satisfied when the difference between the tail pointer and the head pointer is at least equal to an aggregation threshold. The third interrupt generation condition is satisfied when an amount of time that has elapsed since a previous interrupt was issued exceeds a reference time.

Abstract: Provided are method for dynamically allocating resources to command queues and response queues by a non-volatile memory (NVM) controller. The method includes creating command queues and response queues for at least one operating system among a plurality of operating systems running on a host system and mapping the created command queues and response queues to a plurality of internal shared queue registers. The plurality of operating systems running on the host system communicate with at least one NVM controller independently.