Patents by Inventor Sarathy Jayakumar
Sarathy Jayakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12223308Abstract: Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.Type: GrantFiled: August 25, 2020Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Mohan Kumar, Sarathy Jayakumar, Brett Peng Wang, Ashok Raj, Murugasamy Nachimuthu
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Patent number: 12164906Abstract: A modular microcode (uCode) patch method to support runtime persistent update and associated apparatus. The method enables BIOS uCode patches to be received during platform runtime operations and written to first and second uCode extension regions as uCode images for a firmware device layout that further includes a uCode base region in which a current uCode image is stored. Following a platform reset, the first and second uCode extension regions are inspected to determine if one or more valid and newer uCode images (than the current uCode image) are present. If so, the newest uCode image is booted rather than the current uCode image. Following a successful boot, the newest uCode image is copied to the uCode base region to sync-up the current uCode image to the newest version. In one aspect, received uCode images are written to the first and second uCode extension regions in an alternating manner to support roll-back.Type: GrantFiled: February 26, 2020Date of Patent: December 10, 2024Assignee: Intel CorporationInventors: Mohan J. Kumar, Sarathy Jayakumar, Chuan Song, Ruixia Li, Siyuan Fu, Jiaxin Wu, Lui He
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Patent number: 12130924Abstract: Methods and apparatus for seamless SMM (System Management Mode) global driver update base on SMM Root-of-Trust. Mechanisms are provided to load and replace SMM drivers at runtime in a secure manner, without requiring an SMM firmware update and platform reset. SMM code is executed by BIOS during boot in a hidden area of memory called SMRAM space. Seamless update using an SMM Global Driver Update provides a method to load and replace all SMM drivers (including SMM infrastructure) on an already shipped platform production for purposes such as bug fixes. The principles and teachings may also be applied to update other types of secure execution mode code in addition to SMM code.Type: GrantFiled: December 26, 2020Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Sarathy Jayakumar, Jiewen Yao, Murugasamy K Nachimuthu, Ruixia Li, Siyuan Fu
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Publication number: 20240320002Abstract: An apparatus and method for a more efficient system management mode. For example, one embodiment of a processor comprises: a plurality of cores, at least a first core of the plurality of cores to perform operations to cause the plurality of cores to enter into a system management mode (SMM), the operations comprising: allocating a memory region for a system management RAM (SMRAM); writing an SMRAM state save location to a first register; and generating a page table in the SMRAM, including mapping a virtual address space a physical address space.Type: ApplicationFiled: September 29, 2023Publication date: September 26, 2024Inventors: Jay LAWLOR, David SHEFFIELD, Xiang ZOU, Michael KINNEY, Charles HOLTHAUS, Thomas TOLL, Salessawi Ferede YITBAREK, Andreas KLEEN, Keshavan TIRUVALLUR, Sarathy JAYAKUMAR, Ruiyu NI
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Publication number: 20240241805Abstract: A disclosed example includes setting a corrected error threshold value for a memory rank; recording, in a corrected error bank record memory structure, corrected errors for memory banks in the memory rank; maintaining, in the corrected error bank record memory structure, counts of the corrected errors for the memory banks; and notifying runtime error handling circuitry in response to at least one of the counts of the corrected errors satisfying a threshold value.Type: ApplicationFiled: September 25, 2021Publication date: July 18, 2024Inventors: Tao Xu, Shijie Liu, Kevin Yufu Li, Lei Zhu, Sarathy Jayakumar
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Patent number: 12008359Abstract: Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.Type: GrantFiled: February 13, 2020Date of Patent: June 11, 2024Assignee: Intel CorporationInventors: Sarathy Jayakumar, Mohan J. Kumar, Murugasamy K. Nachimuthu, Michael A. Rothman
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Publication number: 20240184621Abstract: Various examples relate to a firmware apparatus (10), firmware device, firmware method, and computer program for a computer system (100) comprising processing circuitry (105), and to a corresponding computer system (100). The firmware apparatus (10) comprises an interface (12) for accessing functionality of the firmware apparatus (10) from an operating system of the computer system (100). The firmware apparatus (10) comprises control circuitry (14), configured to identify one or more processing functionalities being supported by the processing circuitry (105) of the computer system (100), provide information on the one or more processing functionalities via the interface (12) to a user mode interface of the operating system of the computer system (100), and provide access to the one or more processing functionalities for application programs being executed in the operation system, the access being based on the information on the one or more processing functionalities provided to the user mode interface.Type: ApplicationFiled: December 9, 2021Publication date: June 6, 2024Inventors: Sarathy JAYAKUMAR, Zijian YOU, Karthik GOPALAKRISHNAN, Erik KANEDA, Dan WILLIAMS
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Patent number: 11941391Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.Type: GrantFiled: April 6, 2020Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Mohan J. Kumar, Sarathy Jayakumar, Chuan Song, Ruixia Li, Xiaojin Yuan, Haiyue Wang, Chong Han
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Patent number: 11900115Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: GrantFiled: March 27, 2023Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman Strong, Jason Brandt, Rupin Vakharwala, Jeff Huxel, Larisa Novakovsky, Ido Ouziel, Sarathy Jayakumar
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Publication number: 20230401061Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: ApplicationFiled: March 27, 2023Publication date: December 14, 2023Inventors: Ashok RAJ, Andreas KLEEN, Gilbert NEIGER, Beeman STRONG, Jason BRANDT, Rupin VAKHARWALA, Jeff HUXEL, Larisa NOVAKOVSKY, Ido OUZIEL, Sarathy JAYAKUMAR
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Patent number: 11809878Abstract: Systems, apparatuses and methods may provide for technology that stores first hardware related data to a basic input output system (BIOS) memory area and generates a mailbox data structure, wherein the mailbox data structure includes a first identifier-pointer pair associated with the first hardware related data. Additionally, the technology may generate an operating system (OS) interface table, wherein the OS interface table includes a pointer to the mailbox data structure. In one example, the technology also stores second hardware related data to the BIOS memory area at runtime and adds a second identifier-pointer pair to the mailbox data structure at runtime, wherein the second identifier-pointer pair is associated with the second hardware related data.Type: GrantFiled: February 13, 2020Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Sarathy Jayakumar, Mohan Kumar
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Publication number: 20230315575Abstract: Techniques and mechanisms for supporting machine check functionality with a handler which is implemented in firmware. In an embodiment, a processor executes first firmware code to implement a machine check event (MCE) detector. The MCE detector detects a hardware error of a platform which includes the processor, and generates a call to invoke an MCE handler which the processor implements by executing second firmware code. The MCE handler is called, outside of a software context, to attempt a recovery from the hardware error. The call is performed independent of any system management interrupt being based on the detected hardware error. In another embodiment, another MCE handler of an operating system is conditionally invoked where it is determined that the attempted recovery by the first MCE handler was unsuccessful.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Sarathy Jayakumar, Eswar Konduru, John Holm
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Publication number: 20230305834Abstract: Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.Type: ApplicationFiled: August 25, 2020Publication date: September 28, 2023Inventors: Mohan Kumar, Sarathy Jayakumar, Brett Peng Wang, Ashok Raj, Murugasamy Nachimuthu
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Publication number: 20230169171Abstract: Systems, apparatuses and methods may provide technology for managing BIOS modules. The technology may include a boot controller to perform a boot procedure by loading and executing a basic input output system (BIOS) boot module, a setup controller to load and execute a BIOS boot module during runtime (i.e., bypassing reboot) using a changed hardware configuration parameter, and an update controller to load and execute a new or updated BIOS boot module during runtime (i.e., bypassing reboot), where each controller is to operate under direction of an operating system (OS). The technology may perform these BIOS operations within a secure BIOS environment.Type: ApplicationFiled: May 11, 2020Publication date: June 1, 2023Inventors: Sarathy Jayakumar, Zijian You
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Patent number: 11614939Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.Type: GrantFiled: June 25, 2021Date of Patent: March 28, 2023Assignee: Intel CorporationInventors: Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman Strong, Jason Brandt, Rupin Vakharwala, Jeff Huxel, Larisa Novakovsky, Ido Ouziel, Sarathy Jayakumar
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Publication number: 20220350500Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.Type: ApplicationFiled: June 30, 2022Publication date: November 3, 2022Inventors: Wei P. CHEN, Theodros YIGZAW, Sarathy JAYAKUMAR, Anthony LUCK, Deep K. BUCH, Rajat AGARWAL, Kuljit S. BAINS, John G. HOLM, Brent CHARTRAND, Keith KLAYMAN
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Patent number: 11327918Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N?0.Type: GrantFiled: June 29, 2018Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Zhi Yong Chen, Sarathy Jayakumar, Yi Zeng, Wenjuan Mao, Anil Agrawal
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Patent number: 11307996Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.Type: GrantFiled: November 30, 2018Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Sarathy Jayakumar, Ashok Raj, Wei P. Chen, Theodros Yigzaw, John Holm
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Publication number: 20220019444Abstract: An electronic device is disclosed, including a first set of processor cores including at least one processor core and a second set of processor cores including at least one processor core. The electronic device is configured such that during initialization of the electronic device: the first set of processor cores executes first initialization instructions in a first execution environment, the second set of processor cores executes second initialization instructions in a second execution environment, and the first set and the second set at least one of read or write to a shared register.Type: ApplicationFiled: September 28, 2021Publication date: January 20, 2022Inventors: Di ZHANG, Sarathy JAYAKUMAR, Vincent ZIMMER, Fei LI, Bo HE, Zhuangzhi LI, Zhi JIN, Lin CHEN, Guomin JIANG
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Publication number: 20220019426Abstract: Methods, apparatus, and systems for upgradable microcode (uCode) loading and activation in runtime for bare metal deployments that support runtime update of the uCode loading procedure as well as dynamic load of activation procedure(s) specific to uCode patch and activation policy specific to users. The solution provides several advantages, including enabling cloud service providers to hot-patch the uCode through a standalone uCode loader runtime service in BIOS firmware for bare metal deployment without tenant system involvement. The support of runtime update of uCode loading procedures decouples uCode loading logic from uCode loader framework. This removes dependencies on the uCode loader runtime service when needing to update the uCode loading logic.Type: ApplicationFiled: August 3, 2021Publication date: January 20, 2022Inventors: Chuan SONG, Ruixia LI, Murugasamy K. NACHIMUTHU, Mohan J. KUMAR, Sarathy JAYAKUMAR, Xiaojin YUAN, Yidong WU, Siyuan FU, Feng JIANG