Abstract: A method may include operations including, receiving, at an application program interface (API) of a third party computing system, an API call related to a dispute associated with a user of an electronic device, the call being received from an electronic device to invoke a dispute resolution to the dispute. The method may include communicating, by the API in response to the API call, dispute information to dispute resolution intelligence of the third-party computing system. The method may include determining, by the dispute resolution intelligence based on the dispute information, the decision with respect to the dispute, and providing the decision to a callback interface in response to the dispute information having been received from the API. The method may additionally include communicating, by the callback interface to the electronic device identified in response to the dispute information having been received from the API, the decision to the dispute resolution.

Abstract: A method may include operations including, receiving, at an application program interface (API) of a third party computing system, an API call related to a dispute associated with a user of an electronic device, the call being received from an electronic device to invoke a dispute resolution to the dispute. The method may include communicating, by the API in response to the API call, dispute information to dispute resolution intelligence of the third-party computing system. The method may include determining, by the dispute resolution intelligence based on the dispute information, the decision with respect to the dispute, and providing the decision to a callback interface in response to the dispute information having been received from the API. The method may additionally include communicating, by the callback interface to the electronic device identified in response to the dispute information having been received from the API, the decision to the dispute resolution.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A method and apparatus for making angled vias in an integrated circuit package substrate includes providing an integrated circuit package substrate having an upper surface and a lower surface. A first position is selected for a first via opening on the upper surface of the package substrate, and a second position is selected for a second via opening on the lower surface of the package substrate. A selected non-vertical angle is determined for forming an angled via through the first position and the second position. The angled via is formed through the first position and the second position at the selected non-vertical angle.

Abstract: A fuse formed in an integrated circuit die includes: a length of an electrically conductive material for connecting two points of a circuit on the integrated circuit die and for selectively breaking the connection by a pulse of electrical current sufficient to dissolve a portion of the electrically conductive material; a passivation layer formed over the length of electrically conductive material; and a protective coating formed over a portion of the length of electrically conductive material in addition to the passivation layer to avoid damage to the fuse from an etchant during a bumping process.

Abstract: A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

Abstract: A thermal measurement device for obtaining accurate thermal profiles during flip-chip semiconductor packaging and methodologies for making such devices is disclosed. Particularly, a measurement device comprised of a thermocouple sandwiched between a semiconductor packaging substrate and a semiconductor die. Such a device providing increased accuracy in temperature measurement. The present invention also teaches a packaging substrate assembled with a semiconductor die having an opening in the substrate enabling the placement of a thermocouple such that it is in contact with the die and secured in place. Additionally, methods of constructing the devices of the present invention are disclosed.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A substrate which includes an upper and lower surface. The substrate also includes a center or interior portion and a peripheral portion. The upper surface is contoured at the center portion. Solder bumps extend from the upper surface and are positioned in the center portion, and solder bumps extend from the upper surface and are positioned in the peripheral portion. Additional solder material is added to the solder bumps. By adding the additional solder material to the solder bumps, a planar surface is provided by the upper surfaces of the center solder bumps and the peripheral solder bumps. Adding solder to the solder bumps in the periphery portion compensates for the die area planarity differences between the center portion and the periphery portion. As a result of adding solder, planarity issues between the die and the substrate are reduced. Thus, yield losses due to opens in the flipchip joints are also decreased.

Abstract: A method of assembling at least a first integrated circuit and a second integrated circuit into a multi chip module. The first integrated circuit is attached and electrically connected to a first substrate to form a first assembly, which is tested to ensure that it functions properly. The second integrated circuit is attached and electrically connected to a second substrate to form a second assembly, which is also tested to ensure that it functions properly. The first assembly is attached and electrically connected to the second assembly to form the multi chip module.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A package comprises a top die and a bottom die. The top die has top and bottom surfaces while the bottom die has top and bottom surfaces. The bottom die is mounted on a substrate, which has a top surface, such that the bottom surface of the bottom die faces the top surface of the substrate. The bottom surface of the top die is separated from the top surface of the bottom die by an interposer, which creates a space between the exterior regions of the top surface of the bottom die and the bottom surface of the top die. Each of a plurality of wires, which are electrically connected to the bottom die, runs through this space (i.e. runs between the top surface of the bottom die and the bottom surface of the top die), thereby permitting (if desired) the top die to be at least as large as the bottom die.

Abstract: A method for creating a die that has some bond pads that are compatible with wire bonding and others that are compatible with solder bonding. A layer of copper is disposed over aluminum bond pads and selectively removed from those bond pads that are desired to be compatible with wire bonding.

Abstract: Disclosed is a method of planarizing an array of plastically-deformable electrical contacts on an integrated circuit. An integrated circuit is placed on a plate with an array of plastically-deformable electrical contacts substantially parallel to and facing the plate, thereby creating an assembly. The integrated circuit is placed above the plate such that the weight of the integrated circuit bears down on the array of plastically-deformable electrical contacts. The assembly is then heated sufficiently to cause individual ones of the plastically-deformable electrical contacts to locally soften but not to cause said individual ones of the electrical contacts to liquefy throughout their volumes. The weight of the integrated circuit applies a force to the softened plastically-deformable electrical contacts, thereby resulting in their planarization.

Abstract: A method for making a flip chip ball grid array (BGA) package includes the step of thinning a die for matching a composite coefficient of thermal expansion to that of a second level board.

Abstract: A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.