Patents by Inventor Saravana Maruthamuthu
Saravana Maruthamuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230387044Abstract: Integrated circuit (IC) package employing on-package tunable inductor formed in redistribution layer (RDL) for impedance tuner circuit, and related methods. The IC package includes an impedance tuner circuit that includes a tunable inductor that can be tuned to change the frequency response of the impedance tuner circuit. To reduce the circuit area, the tunable inductor is formed in a RDL of a package substrate of the IC package. The IC package also includes a semiconductor die (“die”) that includes other components of the impedance tuner circuit that are coupled to the tunable inductor by the die being coupled to the package substrate. In this manner, by the tunable inductor being formed in a RDL in the package substrate, the signal path lengths between the tunable inductor and other components of the tunable impedance circuit are reduced, thereby reducing inductance path resistance and improving quality (Q) factor of the tunable inductor.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventor: Saravana Maruthamuthu
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Patent number: 11521793Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: GrantFiled: December 15, 2020Date of Patent: December 6, 2022Assignee: Intel CorporationInventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Publication number: 20210273342Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
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Patent number: 11031699Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.Type: GrantFiled: February 9, 2018Date of Patent: June 8, 2021Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
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Publication number: 20210104359Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: ApplicationFiled: December 15, 2020Publication date: April 8, 2021Inventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Patent number: 10896780Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: GrantFiled: March 2, 2018Date of Patent: January 19, 2021Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Patent number: 10872812Abstract: Various embodiments include, for example, a noise suppression filter for a power-delivery network (PDN). In one exemplary embodiment, a capacitor device, which may be used as at least a portion of the noise suppression filter, includes a first conductive plate and a second conductive plate with a dielectric material formed between the first conductive plate and the second conductive plate. A floating conductive fill layer is formed within the dielectric material and between the first conductive plate and the second conductive plate. Other embodiments of capacitors, and methods of forming the capacitor, are disclosed.Type: GrantFiled: March 9, 2018Date of Patent: December 22, 2020Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Shankar Chandrasekaran Jayendra, Shidlingeshwar Khatakalle
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Patent number: 10867934Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.Type: GrantFiled: March 27, 2018Date of Patent: December 15, 2020Assignee: Intel IP CorporationInventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
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Publication number: 20190304922Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas
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Publication number: 20190297758Abstract: An electromagnetic shielding cap for shielding an electrical circuit on a circuit board includes a frame structure and a lid structure containing a passive electrical element structure. The lid structure is attached to the frame structure and further contains at least one contact interface for connecting the passive electrical element structure to an electrical circuit to be shielded by the electromagnetic shielding cap.Type: ApplicationFiled: March 23, 2018Publication date: September 26, 2019Inventors: Sonja KOLLER, Saravana MARUTHAMUTHU, Bernd WAIDHAS
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Publication number: 20190279899Abstract: Various embodiments include, for example, a noise suppression filter for a power-delivery network (PDN). In one exemplary embodiment, a capacitor device, which may be used as at least a portion of the noise suppression filter, includes a first conductive plate and a second conductive plate with a dielectric material formed between the first conductive plate and the second conductive plate. A floating conductive fill layer is formed within the dielectric material and between the first conductive plate and the second conductive plate. Other embodiments of capacitors, and methods of forming the capacitor, are disclosed.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Inventors: Saravana Maruthamuthu, Shankar Chandrasekaran Jayendra, Shidlingeshwar Khatakalle
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Publication number: 20190272950Abstract: A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.Type: ApplicationFiled: March 2, 2018Publication date: September 5, 2019Inventors: Saravana Maruthamuthu, Andreas Augustin, Andreas Wolter
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Publication number: 20190252792Abstract: Some embodiments include packages and methods of making the packages. One of the packages includes a ground layer (e.g., a ground plane) of metal formed over a chip of die, an antenna element of metal formed over the ground layer, and a dielectric lens formed over the antenna element. The dielectric lens includes a plurality of dielectric layers that have graded dielectric constants in a decreasing order along a direction from the antenna element toward a top surface of the package.Type: ApplicationFiled: February 9, 2018Publication date: August 15, 2019Inventors: Saravana Maruthamuthu, Bernd Waidhas, Andreas Augustin, Georg Seidemann
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Patent number: 10319688Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.Type: GrantFiled: December 9, 2013Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Thorsten Meyer, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
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Patent number: 9819327Abstract: Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile communication devices for radio frequency (RF) communication. In some embodiments, a mobile communication device may include an antenna; a transmitter circuit having an output port, a tuner circuit having one or more BAWRs, an antenna port coupled to the antenna, a transmitter port coupled to the output port of the transmitter circuit, and a control port; and a control circuit, coupled to the control port, configured to adjust an impedance of the tuner circuit, via adjustment of a BAWR or another component of the tuner circuit, based at least in part on an impedance of the antenna. Other embodiments may be described and/or claimed.Type: GrantFiled: June 26, 2013Date of Patent: November 14, 2017Assignee: INTEL IP CORPORATIONInventors: Saravana Maruthamuthu, Thorsten Meyer, Pablo Herrero, Andreas Wolter, Georg Seidemann, Mikael Knudsen, Pauli Jaervinen
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Publication number: 20160284461Abstract: An apparatus including a device including a primary winding and a secondary winding interwound and magnetically coupled in two metal layers, wherein an inductance of one of the primary winding and the secondary winding is tuned for a target inductance ratio between the primary winding and the secondary winding. A method including forming an impedance matched transformer device on a substrate including a primary winding and a secondary winding interwound and magnetically coupled in two metal layers in a laterally coupled layout, wherein an inductance of one of the primary winding and the secondary winding is tuned for a target inductance ratio between the primary winding and the secondary winding.Type: ApplicationFiled: March 28, 2015Publication date: September 29, 2016Inventor: Saravana Maruthamuthu
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Publication number: 20160240492Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.Type: ApplicationFiled: December 9, 2013Publication date: August 18, 2016Inventors: Andreas Wolter, Saravana Maruthamuthu, Mikael Knudsen, Meyer Thorsten, Georg Seidemann, Pablo Herrero, Pauli Jaervinen
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Publication number: 20150333401Abstract: Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile communication devices for radio frequency (RF) communication. In some embodiments, a mobile communication device may include an antenna; a transmitter circuit having an output port, a tuner circuit having one or more BAWRs, an antenna port coupled to the antenna, a transmitter port coupled to the output port of the transmitter circuit, and a control port; and a control circuit, coupled to the control port, configured to adjust an impedance of the tuner circuit, via adjustment of a BAWR or another component of the tuner circuit, based at least in part on an impedance of the antenna. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 26, 2013Publication date: November 19, 2015Inventors: Saravana MARUTHAMUTHU, Thorsten MEYER, Pablo HERRERO, Andreas WOLTER, Georg SEIDEMANN, Mikael KNUDSEN, Pauli JAERVINEN
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Patent number: 8779564Abstract: A semiconductor device may include: a chip; a chip packaging structure at least partially surrounding the chip and having a receiving region configured to receive a first capacitive coupling structure; a first capacitive coupling structure disposed in the receiving region; and a second capacitive coupling structure disposed over the first capacitive coupling structure and capacitively coupled to the first capacitive coupling structure.Type: GrantFiled: March 14, 2013Date of Patent: July 15, 2014Assignee: Intel IP CorporationInventors: Mikael Knudsen, Thorsten Meyer, Saravana Maruthamuthu, Andreas Wolter, Georg Seidemann, Pablo Herrero, Pauli Jaervinen