Patents by Inventor Saravanakkumar RADHAKRISHNAN

Saravanakkumar RADHAKRISHNAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12267182
    Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: April 1, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Patent number: 12028192
    Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: July 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Publication number: 20240106688
    Abstract: A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Saravanakkumar Radhakrishnan, Raghu Ganesan
  • Publication number: 20230417529
    Abstract: An example first device includes: processor circuitry configured to establish a cable communication; analog to digital converter circuitry configured to sample cable voltages over time; echo estimator circuitry configured to determine a plurality of echo coefficients corresponding to the plurality of voltages; and physical length estimator circuitry configured to: identify a first echo coefficient in the echo coefficients that satisfies a static threshold, the first echo coefficient corresponding to a near end echo; identify a second echo coefficient in the echo coefficients that satisfies a dynamic threshold, the second echo coefficient corresponding to a far end echo; and estimate the length of a cable for the cable communication based on the first echo coefficient and the second echo coefficient.
    Type: Application
    Filed: November 30, 2022
    Publication date: December 28, 2023
    Inventors: Raghu Ganesan, Rallabandi Annapurna, Sucheth S. Kuncham, Saravanakkumar Radhakrishnan, Sumantra Seth, Geet Modi
  • Publication number: 20230208675
    Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.
    Type: Application
    Filed: March 6, 2023
    Publication date: June 29, 2023
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Publication number: 20230208685
    Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 29, 2023
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Publication number: 20230136070
    Abstract: Methods, apparatus, and systems to synchronize Ethernet signals are disclosed. An example apparatus includes slicer circuitry having an input coupled to interface circuitry and having an output, the slicer circuitry configured to receive an analog signal corresponding to a first Analog to Digital Converter (ADC) clock in a plurality of ADC clocks and operable to determine symbols based on the analog signal; logic circuitry to determine whether there is a symbol transition in the symbols; timing error detector circuitry to update an error value in response to the determination that there is a symbol transition; timing loop circuitry to determine a frequency of voltage oscillations based on at least the error value; and phase interpolator circuitry to change a plurality of phase parameters corresponding to the plurality of ADC clocks at a rate given by the frequency of voltage oscillations.
    Type: Application
    Filed: April 26, 2022
    Publication date: May 4, 2023
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan
  • Patent number: 11601302
    Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: March 7, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Patent number: 11595064
    Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: February 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal, Rallabandi V Lakshmi Annapurna
  • Patent number: 11588667
    Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Patent number: 11469785
    Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 11, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Ganesan, Gaurav Aggarwal, Rahul Koppisetti, Rallabandi V Lakshmi Annapurna, Saravanakkumar Radhakrishnan, Kalpesh Laxmanbhai Rajai
  • Patent number: 11374601
    Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 28, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Kalpesh Laxmanbhai Rajai, Soumyajit Roul, Sumantra Seth
  • Patent number: 11316707
    Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kalpesh Laxmanbhai Rajai, Saravanakkumar Radhakrishnan, Gaurav Aggarwal, Raghu Ganesan, Rallabandi V Lakshmi Annapurna
  • Publication number: 20220070031
    Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 3, 2022
    Inventors: Raghu Ganesan, Saravanakkumar Radhakrishnan, Gaurav Aggarwal
  • Publication number: 20220052714
    Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 17, 2022
    Inventors: Raghu GANESAN, Saravanakkumar RADHAKRISHNAN, Gaurav AGGARWAL, Rallabandi V Lakshmi ANNAPURNA
  • Publication number: 20210288826
    Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 16, 2021
    Inventors: Kalpesh Laxmanbhai RAJAI, Saravanakkumar RADHAKRISHNAN, Gaurav AGGARWAL, Raghu GANESAN, Rallabandi V. Lakshmi ANNAPURNA
  • Publication number: 20210288656
    Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 16, 2021
    Inventors: Raghu GANESAN, Saravanakkumar RADHAKRISHNAN, Kalpesh Laxmanbhai RAJAI, Soumyajit ROUL, Sumantra SETH
  • Publication number: 20210288684
    Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 16, 2021
    Inventors: Raghu GANESAN, Gaurav AGGARWAL, Rahul KOPPISETTI, Rallabandi V Lakshmi ANNAPURNA, Saravanakkumar RADHAKRISHNAN, Kalpesh Laxmanbhai RAJAI