Patents by Inventor Saravanakkumar Swaminathan RADHAKRISHNAN

Saravanakkumar Swaminathan RADHAKRISHNAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210014087
    Abstract: A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Raghu GANESAN, Kalpesh Laxmanbhai RAJAI, Saravanakkumar Swaminathan RADHAKRISHNAN
  • Patent number: 10833895
    Abstract: A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: November 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Ganesan, Kalpesh Laxmanbhai Rajai, Saravanakkumar Swaminathan Radhakrishnan
  • Publication number: 20200092144
    Abstract: A device includes a receiver having analog front-end circuitry and a digital signal processing (DSP) circuit. The DSP circuit is configured to select one of a plurality of digital equalization (DEQ) filter options and to perform DEQ operations based on the selected DEQ filter option, wherein the DSP circuit is configured to select one of the plurality of DEQ filter options based on a channel length estimate and a plurality of different sets of DEQ filter coefficients predetermined for different channel lengths.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 19, 2020
    Inventors: Raghu GANESAN, Kalpesh Laxmanbhai RAJAI, Saravanakkumar Swaminathan RADHAKRISHNAN