Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.

Abstract: A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off , during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.

Abstract: A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration.

Abstract: A receiver includes LNA-mixer arrangement, a current buffer arrangement and an analog filter arrangement. The LNA-mixer arrangement receives a plurality of input signals and provides a wide-band input match for a specified frequency range of operation. The LNA-mixer arrangement includes a plurality of LNA structures and a plurality of mixer structures where each of the LNA structure path is coupled to a single mixer structure. The LNA-mixer arrangement outputs a first signal. The current buffer arrangement receives the first signal and reduces the Image Rejection (IR) asymmetry between the high frequency portion and the low frequency portion of the first signal as well as provides a gain to the first signal. The current buffer arrangement outputs a second signal. The analog filter arrangement receives the second signals and perform filtering and calibration.

Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.

Abstract: An integrated circuit with multiple supply voltage domains includes a first domain and a second domain of electrical components. The first domain receives current from a first voltage rail and discharges electrical current to a second voltage rail. A second domain of electrical components receives current from the second voltage rail and discharges electrical current to a third voltage rail at a third voltage. An external voltage source provides a supply voltage across the first voltage rail and the third voltage rail. The integrated circuit further includes a regulator for regulating the second voltage rail. The circuit domains are divided into granules that can be multiplexed between domains when the supply voltage fluctuations are too large and too long for the regulator to handle. This concept may be extended to include additional domains of electrical components.

Abstract: A device comprises an active-pull-up stage and an active-pull-down stage. The device receives at least one reference voltage and provides an regulated output voltage to at least one load. The active-pull-up and active-pull-down stages are adapted to source or sink a current delivered to or received from the at least one load to regulate the output voltage provided to the at least one load. Other embodiments and methods are also claimed and described.

Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.

Abstract: A series voltage regulator circuit includes first and second voltage regulators, a first controller to control an output voltage of the first voltage regulator, and a second controller to control an output voltage of the second voltage regulator. The voltage regulators preferably include internal control loops which rapidly respond to the load variations, however the controllers operate independently from these variations. By isolating the controllers from the load, the controllers are able to maintain the output of the regulators at a constant value. In one embodiment, the voltage regulators are connected in a push-pull configuration for driving the load.

Abstract: An integrated circuit with multiple supply voltage domains includes a first domain and a second domain of electrical components. The first domain receives current from a first voltage rail and discharges electrical current to a second voltage rail. A second domain of electrical components receives current from the second voltage rail and discharges electrical current to a third voltage rail at a third voltage. An external voltage source provides a supply voltage across the first voltage rail and the third voltage rail. The integrated circuit further includes a regulator for regulating the second voltage rail. The circuit domains are divided into granules that can be multiplexed between domains when the supply voltage fluctuations are too large and too long for the regulator to handle. This concept may be extended to include additional domains of electrical components.