Patents by Inventor Saravanan

Saravanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8874979
    Abstract: According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Anil B. Lingambudi, Saravanan Sethuraman, Kenneth L. Wright
  • Patent number: 8872322
    Abstract: Disclosed is a stacked chip module and associated method with integrated circuit (IC) chips having integratable built-in self-maintenance blocks. The module comprises a stack of chips and each chip comprises a self-maintenance block with first and second controllers. The first controller controls wafer-level and module-level servicing (e.g., self-testing or self-repairing) of an on-chip functional block. The second controller provides an interface between an off-chip tester and the first controller during wafer-level servicing. Each chip further comprises a plurality of interconnect structures (e.g., multiplexers and through-substrate-vias) that integrate the self-maintenance blocks of adjacent chips in the stack so that, during module-level servicing, a single second controller on a single one of the chips in the stack (e.g., the bottom chip) provides the only interface between the off-chip tester and all of the first controllers.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Gorman, Derek H. Leu, Krishnendu Mondal, Saravanan Sethuraman
  • Patent number: 8874541
    Abstract: Methods, systems, and computer program products for identifying search keywords for searching for an online information resource are disclosed. The method involves receiving a request, from a business, for search keywords relating to the content of the business's online information resource. The method further involves generating a post including a link to a search keyword recommendation page; and publishing, using a social network application, the post to a newsfeed in a social network. Additionally, the method involves receiving, from social network users, a plurality of search keywords relating to the online information resource's content. In addition, the method involves ranking the received search keywords; and presenting, to the business, the most popular search keywords.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: October 28, 2014
    Assignee: Intuit Inc.
    Inventors: Jeremy G. Vandehey, Saravanan Coimbatore
  • Publication number: 20140315244
    Abstract: A fungal strain Beauveria species bearing accession number MTCC 5184 is disclosed. The process for the preparation of an enzyme mix including at least one enzyme selected from, but not limited to protease, carbohydrase, and lipase from the disclosed Beauveria species and uses of the enzyme mix in various areas also disclosed.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 23, 2014
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Seeta Laxman RYALI, Shiv Shankar, Snehal Vijay More, Harish Bansilal Khandelwal, Chandra Babu Kannan Narasimhan, Saravanan Palanivel, Padmanabhan Balaram
  • Publication number: 20140317473
    Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
    Type: Application
    Filed: April 22, 2013
    Publication date: October 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Patent number: 8869007
    Abstract: According to one embodiment of the present invention, a method for operating a three dimensional (ā€œ3Dā€) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Anil B. Lingambudi, Saravanan Sethuraman, Kenneth L. Wright
  • Publication number: 20140307008
    Abstract: An image display unit for displaying still or moving images, this unit having at least one ambient light sensor which is configured to detect a color and an intensity of an ambient light in the surroundings of the image display unit and this unit also having an intensity control device which is configured to adjust the intensity of each individual image point in the images displayed by the image display unit based on the detected color and intensity of the ambient light. Also described is a related mobile phone and a related method.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 16, 2014
    Applicant: Robert Bosch GmbH
    Inventors: Christoph DELFS, Saravanan JAYAPRAKASH
  • Patent number: 8853847
    Abstract: Disclosed is a stacked chip module incorporating a stack of integrated circuit (IC) chips having integratable and automatically reconfigurable built-in self-maintenance blocks (i.e., built-in self-test (BIST) circuits or built-in self-repair (BISR) circuits). Integration of the built-in self-maintenance blocks between the IC chips in the stack allows for servicing (e.g., self-testing or self-repairing) of functional blocks at the module-level. Automatic reconfiguration of the built-in self-maintenance blocks further allows for functional blocks on any of the IC chips in the stack to be serviced at the module-level even when one or more controllers associated with a given built-in self-maintenance block on a given IC chip has been determined to be defective (e.g., during previous wafer-level servicing). Also disclosed is a method of manufacturing and servicing such a stacked chip module.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Gorman, Krishnendu Mondal, Saravanan Sethuraman
  • Publication number: 20140293810
    Abstract: The present disclosure is related to a method for identifying optimal influential paths in a distributed network for transmitting information/request to one or more target nodes. The routing server at the source node identifies one or more target nodes in the network based on information. Thereafter, routing server identifies one or more optimal nodes based on influence value associated with each node in network and determines predicted action that will be performed by the optimal node and transmits the information to each optimal node. Each optimal node performs an action upon receiving the information from the source node. The routing server receives the data related to the operation performed and updates influence value associated with respective nodes. The routing server identifies one or more optimal paths based on one of the influence value being updated and the action performed by each optimal node.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 2, 2014
    Inventors: Ajay Kumar NEMA, Manish Kumar NEMA, Mohan Kumar PANDIAN, Roopesh Kumar NEMA, Saravanan SOUPRAMANIANE, Siva Kiran DHULIPALA, Vinoo M. CHACKO
  • Publication number: 20140297887
    Abstract: The present disclosure is related to a method for transmitting information on priority basis to one or more nodes in distributed network. The routing server at source node generates one or more set of nodes from plurality of nodes based on reputation value. The routing server identifies first set of nodes with highest reputation value, determines predicted action to be perforrmed by each node. The routing server transmits information to each node in first set. Each node performs an action. The routing server computes the difference between the predicted action and action performed by each node in the first set and updates the reputation value of each node in the first set. Thereafter, routing server transmits the information the second set, third set and so on.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 2, 2014
    Applicant: WHISTLE TALK TECHNOLOGIES PVT. LTD.
    Inventors: Ajay Kumar NEMA, Manish Kumar NEMA, Mohan Kumar PANDIAN, Roopesh Kumar NEMA, Saravanan SOUPRAMANIANE, Siva Kiran DHULIPALA, Vinoo M. CHACKO
  • Patent number: 8848470
    Abstract: A method and apparatus for continued operation of a memory module, including a first and second memory device, when one of memory devices has failed. The method includes receiving a write operation request to write a data word, having first and second sections, by a first memory module. The memory module may have a first memory device and a second memory device, for respectively storing the first and second sections of the data word. A determination if one of the first and second memory devices is inoperable is made. If one of the first and second memory devices is inoperable, a write operation is performed by writing the first and second sections of the data word to the operable one of the first and second memory devices.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj, Saravanan Sethuraman
  • Publication number: 20140289488
    Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.
    Type: Application
    Filed: March 21, 2013
    Publication date: September 25, 2014
    Applicant: International Business Machines Corporation
    Inventors: Brian J. Connolly, Joab D. Henderson, Jeffrey A. Sabrowski, Sethuraman Saravanan, Kenneth L. Wright
  • Patent number: 8841597
    Abstract: An optical proximity sensor and housing for the same are disclosed. The housing is provided with at least two support structures and at least two modules. A first of the support structures transfers vertical forces applied to one end of a module to an opposite end of the opposite module. A second of the support structures inhibits a pivoting of the modules about the first support structure.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: September 23, 2014
    Assignee: Avago Technologies IP (Singapore) Pte. Ltd.
    Inventors: James Costello, Wee Sin Tan, Kai Koon Lee, Rani Saravanan
  • Publication number: 20140269404
    Abstract: A method and system are described for determining the reliability of the communications between a portable electronic device and an access point (AP) before associating with the AP. In the described embodiments, a first probe request frame is transmitted to the AP at a first data rate, and a first probe response frame is received from the AP, wherein the first probe response frame is responsive to the first probe request frame. Then, a second probe request frame is transmitted to the AP at a second data rate, wherein the first data rate is lower than the second data rate. Then, the portable electronic device determines if a second probe response frame is received from the AP, wherein the second probe response frame is responsive to the second probe request frame. The portable electronic device then determines the reliability of the communications between the portable electronic device and the AP.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 18, 2014
    Applicant: Apple Inc.
    Inventors: Saravanan Balasubramaniyan, Kapil Chhabra, Tito Thomas
  • Publication number: 20140269682
    Abstract: A voice over Internet protocol communication system and method provides infrastructure components as intermediaries between networks, the components include multi-protocol session controllers and a multi-protocol signaling switch as well as a management system. The session controllers process calls and participate in the calls that flow through it. The session controllers process calls that are either at the edge of the network or at the core of the voice over Internet protocol network. The session controllers associate calls with one another in call peers for incoming calls as ingress call peers and for outgoing calls as egress call peers. A centralized database of call routing policies is provided to the session controllers. The session controllers provide cost management, topology hiding, and inter-working, or conversion, of calls from SIP networks to H.323 networks for both voice and video.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: GENBAND US LLC
    Inventors: Sridhar Ramanchandran, Paritosh Tyagi, Saravanan Mallesan, Gaurav Kulshreshtha, Rohini Raman, Medhavi Bhatia, Sohan Shetty
  • Publication number: 20140280696
    Abstract: In a system and method to allow a user to download multiple files in a SharePoint environment, the system includes a detection module configured to detect a selection of at least one item from a document library by a user. The item can be one or more of a file or folder including groups of files. The system further includes a packaging module configured to package the at least one item as a zip file. Furthermore, the system includes a downloading module configured to download the zip file.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: Unisys Corporation
    Inventors: Saravanan Veeramani, Sahana Neeralike
  • Patent number: 8833165
    Abstract: The miniaturized piezoelectric accelerometer includes a support frame (102) having a cavity (104) and a seismic mass (108) supported by a plurality of suspension beams (110) extending from the support frame (102). Each of the suspension beams (110) has a piezoelectric thin film coated on a top surface thereof, with a pair of inter-digital electrodes (114) deposited on an upper surface of each piezoelectric thin film. The presence of acceleration excites bending and thus strain in the piezoelectric thin film, which in turn causes electrical signals to be generated over terminals of the electrodes (114). To collect constructively the output of the electrodes (114), one terminal of each of the electrodes (114) is routed to and electrically connected at a top surface (308) of the seismic mass (108).
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: September 16, 2014
    Assignee: Agency for Science, Technology and Research
    Inventors: Kui Yao, Saravanan Shanmugavel, Trung Dung Luong, Ajit S. Gaunekar, Hon Yu Peter Ng
  • Publication number: 20140250969
    Abstract: A MEMS sensor includes a micro-electromechanical structure, a detection circuit, and a self-test circuit to test the health of the MEMS sensor during runtime operations. The self-test circuit is configured to inject into the micro-electromechanical structure a plurality of injected test signals that are broad-band frequency-varying frequency signals, which are based on spread spectrum based modulation. The injected test signals may a magnitude that is below an observable threshold of the sensor signal as well as a test-signal bandwidth that overlaps with a substantial portion of the sensor bandwidth, including the stimulus of interest.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: ANALOG DEVICES TECHNOLOGY
    Inventors: Kamatchi Saravanan Alagarsamy, William A. Clark, Jishnu Choyi, James M. Lee, Vikas Choudhary
  • Patent number: 8832674
    Abstract: Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient. The off-heap store may be provided in connection with a Java-based environment, and garbage collection may be completely or nearly completely avoided for the off-heap store. The off-heap store may be integrated into a tiered storage solution in certain example embodiments.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Software AG USA, Inc.
    Inventors: Steven T. Harris, Christopher Dennis, Saravanan Subbiah
  • Publication number: 20140250340
    Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman