Patents by Inventor Saravanapriyan Sriraman

Saravanapriyan Sriraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10254641
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: April 9, 2019
    Assignee: Lam Research Corporation
    Inventors: Julien Mailfert, Saravanapriyan Sriraman, Mehmet Derya Tetiker
  • Patent number: 10249511
    Abstract: An inductively coupled plasma processing apparatus comprises a vacuum chamber, a vacuum source, and a substrate support on which a semiconductor substrate is supported. A ceramic showerhead forms an upper wall of the vacuum chamber. The ceramic showerhead includes a gas plenum in fluid communication with a plurality of showerhead gas outlets for supplying process gas to the interior of the vacuum chamber, and a central opening configured to receive a central gas injector. A central gas injector is disposed in the central opening of the ceramic showerhead. The central gas injector includes a plurality of gas injector outlets for supplying process gas to the interior of the vacuum chamber. An RF energy source energizes the process gas into a plasma state to process the semiconductor substrate. The flow rate of the process gas supplied by the central gas injector and the flow rate of the process gas supplied by the ceramic showerhead can be independently controlled.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 2, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Saravanapriyan Sriraman, Alexander Paterson
  • Patent number: 10242845
    Abstract: A substrate is positioned on a substrate support structure within a plasma processing volume of an inductively coupled plasma processing chamber. A first radiofrequency signal is supplied from a first radiofrequency signal generator to a coil disposed outside of the plasma processing volume to generate a plasma in exposure to the substrate. A second radiofrequency signal is supplied from a second radiofrequency signal generator to an electrode within the substrate support structure. The first and second radiofrequency signal generators are controlled independent of each other. The second radiofrequency signal has a frequency greater than or equal to about 27 megaHertz. The second radiofrequency signal generates supplemental plasma density at a level of the substrate within the plasma processing volume while generating a bias voltage of less than about 200 volts at the level of the substrate.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: March 26, 2019
    Assignee: Lam Research Corporation
    Inventors: Zhongkui Tan, Yiting Zhang, Qian Fu, Qing Xu, Ying Wu, Saravanapriyan Sriraman, Alex Paterson
  • Publication number: 20190049937
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Patent number: 10197908
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: February 5, 2019
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho
  • Patent number: 10163610
    Abstract: An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 25, 2018
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Tom A. Kamp, Alexander Paterson
  • Publication number: 20180314148
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 1, 2018
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Richard Wise
  • Publication number: 20180260509
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 13, 2018
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20180247796
    Abstract: In one embodiment, a plasma processing device may include a dielectric window, a vacuum chamber, an energy source, and at least one air amplifier. The dielectric window may include a plasma exposed surface and an air exposed surface. The vacuum chamber and the plasma exposed surface of the dielectric window can cooperate to enclose a plasma processing gas. The energy source can transmit electromagnetic energy through the dielectric window and form an elevated temperature region in the dielectric window. The at least one air amplifier can be in fluid communication with the dielectric window. The at least one air amplifier can operate at a back pressure of at least about 1 in-H2O and can provide at least about 30 cfm of air.
    Type: Application
    Filed: May 2, 2018
    Publication date: August 30, 2018
    Inventors: Jon MCCHESNEY, Saravanapriyan SRIRAMAN, Richard A. MARSH, Alexander Miller PATERSON, John HOLLAND
  • Publication number: 20180240677
    Abstract: Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases. The diffusive flow of the tuning gas enables the tuning gas to be dissociated by the RF power allowing for control of the local residence time variation and preferential spatial dissociation patterns with respect to the local residence time of the reactant gas.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Saravanapriyan Sriraman, Monica Titus, Alex Paterson
  • Publication number: 20180204708
    Abstract: A substrate is positioned on a substrate support structure within a plasma processing volume of an inductively coupled plasma processing chamber. A first radiofrequency signal is supplied from a first radiofrequency signal generator to a coil disposed outside of the plasma processing volume to generate a plasma in exposure to the substrate. A second radiofrequency signal is supplied from a second radiofrequency signal generator to an electrode within the substrate support structure. The first and second radiofrequency signal generators are controlled independent of each other. The second radiofrequency signal has a frequency greater than or equal to about 27 megaHertz. The second radiofrequency signal generates supplemental plasma density at a level of the substrate within the plasma processing volume while generating a bias voltage of less than about 200 volts at the level of the substrate.
    Type: Application
    Filed: January 17, 2017
    Publication date: July 19, 2018
    Inventors: Zhongkui Tan, Yiting Zhang, Qian Fu, Qing Xu, Ying Wu, Saravanapriyan Sriraman, Alex Paterson
  • Patent number: 9996647
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20180157161
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 7, 2018
    Inventors: Julien Mailfert, Saravanapriyan Sriraman, Mehmet Derya Tetiker
  • Publication number: 20180156489
    Abstract: A chamber is provided. The chamber includes a Faraday shield positioned above a substrate support of the chamber. A dielectric window is disposed over the Faraday shield, and the dielectric window has a center opening. A hub having an internal plenum for passing a flow of fluid received from an input conduit and removing the flow of fluid from an output conduit is further provided. The hub has sidewalls and a center cavity inside of the sidewalls for an optical probe, and the internal plenum is disposed in the sidewalls. The hub has an interface surface that is in physical contact with a back side of the Faraday shield. The physical contact provides for a thermal couple to the Faraday shield at a center region around said center opening, and an outer surface of the sidewalls of the hub are disposed within the center opening of the dielectric window.
    Type: Application
    Filed: January 31, 2018
    Publication date: June 7, 2018
    Inventors: Saravanapriyan Sriraman, John Drewery, Jon McChesney, Alex Paterson
  • Patent number: 9978565
    Abstract: In one embodiment, a plasma processing device may include a dielectric window, a vacuum chamber, an energy source, and at least one air amplifier. The dielectric window may include a plasma exposed surface and an air exposed surface. The vacuum chamber and the plasma exposed surface of the dielectric window can cooperate to enclose a plasma processing gas. The energy source can transmit electromagnetic energy through the dielectric window and form an elevated temperature region in the dielectric window. The at least one air amplifier can be in fluid communication with the dielectric window. The at least one air amplifier can operate at a back pressure of at least about 1 in-H2O and can provide at least about 30 cfm of air.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: May 22, 2018
    Assignee: Lam Research Corporation
    Inventors: Jon McChesney, Saravanapriyan Sriraman, Ricky Marsh, Alex Paterson, John Holland
  • Patent number: 9966270
    Abstract: Methods, systems, and computer programs are presented for controlling gas flow in a semiconductor manufacturing chamber. The method includes flowing a reactant gas thorough an inner feed and a tuning gas through an outer feed surrounding the inner feed, such that the gases do not mix until both are introduced in the chamber. Further, the flow of the reactant gas is convective, and the flow of the tuning gas is directed at an angle from the direction of the reactant gas, providing a delivery of the tuning gas in closer proximity to the RF power before further mixing with the reactant gas. Radio frequency power is provided to the electrode to ignite a plasma using the reactant and tuning gases.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 8, 2018
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Monica Titus, Alex Paterson
  • Publication number: 20180053629
    Abstract: A substrate support in a substrate processing system includes an inner portion and an outer portion. The inner portion is positioned below a gas distribution device configured to direct first process gases toward the inner portion. The outer portion includes an edge ring positioned around an outer perimeter of the inner portion to at least partially surround the inner portion and a substrate arranged on the inner portion. The edge ring is configured to be raised and lowered relative to the inner portion, and to direct second process gases toward the inner portion. A controller determines distribution of material deposited on the substrate during processing and, based on the determined distribution, selectively adjusts a position of the edge ring and selectively adjusts flow of at least one of the first process gases and the second process gases.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 22, 2018
    Inventors: Yiting Zhang, Saravanapriyan Sriraman, Alex Paterson
  • Patent number: 9885493
    Abstract: A processing chamber and a Faraday shield system for use in a plasma processing chambers are provided. One system includes a disk structure defining a Faraday shield, and the disk structure has a process side and a back side. The disk structure extends between a center region to a periphery region. The disk structure resides within the processing volume. The system also includes a hub having an internal plenum for passing a flow of air received from an input conduit and removing the flow of air from an output conduit. The hub has an interface surface that is coupled to the back side of the disk structure at the center region. A fluid delivery control is coupled to the input conduit of the hub. The fluid delivery control is configured with a flow rate regulator. The regulated air can be amplified or compressed dry air (CDA).
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: February 6, 2018
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, John Drewery, Jon McChesney, Alex Paterson
  • Publication number: 20170371991
    Abstract: Disclosed are methods of optimizing a computer model which relates the etch profile of a feature on a semiconductor substrate to a set of independent input parameters (A), via the use of a plurality of model parameters (B). In some embodiments, the methods may include modifying one or more values of B so as to reduce a metric indicative of the differences between computed reflectance spectra generated from the model and corresponding experimental reflectance spectra with respect to one or more sets of values of A. In some embodiments, calculating the metric may include an operation of projecting the computed and corresponding experimental reflectance spectra onto a reduced-dimensional subspace and calculating the difference between the reflectance spectra as projected onto the subspace. Also disclosed are etch systems implementing such optimized computer models.
    Type: Application
    Filed: September 7, 2017
    Publication date: December 28, 2017
    Inventors: Mehmet Derya Tetiker, Saravanapriyan Sriraman, Andrew D. Bailey, III, Alex Paterson, Richard A. Gottscho
  • Publication number: 20170363950
    Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 21, 2017
    Inventors: Saravanapriyan Sriraman, Richard Wise, Harmeet Singh, Alex Paterson, Andrew D. Bailey, III, Vahid Vahedi, Richard A. Gottscho