Abstract: A sense circuit suitable for use with semiconductor memory arrays which, in contrast to sense circuits of similar type, exhibits no voltage offset in the latched condition between the input-output (I/O) nodes and the supply lines. The sense circuit includes first and second complementary inverters with inputs connected to first and second I/O nodes, respectively, and with outputs capable of being clamped to one or the other of the two supply lines powering the inverters. Selectively and sequentially enabled cross-coupling transmission gates are connected between the output of each inverter and the input to the other inverter, and selectively enabled biasing transmission gates are connected between the input and output of each inverter. In the operation of the circuit, the two input nodes are first precharged to a predetermined value by enabling the biasing gates. A signal is then applied to one I/O node causing its potential to vary from its quiescent value.

Abstract: The gate of an IGFET, which is directly connected to the input terminal of a circuit is protected by means of first and second diodes connected between the gate and first and second points of operating potential, respectively. The first diode is poled to conduct current in the forward direction when the potential at the gate is more positive than the potential at the first point and the second diode is poled to conduct current in the forward direction when the potential at the gate is more negative than the potential at the second point. A high conductivity diode means is connected between the first and second points of potential. The reverse breakdown voltage (V.sub.R) of the first and second diodes is greater than the V.sub.R of the diode means whereby the first and second diodes conduct only in the forward direction while the diode means conducts in the forward or reverse direction.

Abstract: An oscillator which includes a complementary symmetry metal oxide semiconductor (CMOS) inverter, a crystal connected between the input and output terminals of the inverter, and input and output capacitors connected to these input and output terminals, respectively. Low power dissipation is achieved by making the input capacitance of much higher value than the output capacitance. Frequency stability is obtained by incorporating a voltage controlled capacitor in the circuit which, in response to a change in operating voltage, changes value in a sense to compensate for the tendency of the oscillator frequency to change.

Abstract: A memory cell utilizing first and second cross-coupled CMOS inverters connected to a digit line. During a read command, one inverter is disconnected from the input node of the other inverter to prevent loss of the stored information.