Patents by Inventor Sarion C. S. Lee

Sarion C. S. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6699788
    Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: March 2, 2004
    Assignee: Chartered Semiconductors Manufacturing Limited
    Inventors: Guy Eristoff, Sarion C. S. Lee, Liew San Leong, Goh Khoon Meng
  • Publication number: 20030096499
    Abstract: An integrated nucleation and bulk deposition process is disclosed for forming a CVD metal film over a semiconductor substrate that has structures formed thereon. In the integrated deposition process of the present invention, nucleation seed deposition and bulk deposition are performed in an integrated and contemporaneous manner. In one embodiment, a reactant gas and a reducing agent gas flow into a pressurized reaction chamber. As the integrated deposition process progresses, pressure and flow of reactant gas are increased while flow of reducing agent gas is decreased. The integrated deposition process of the present invention gives a significant decrease in process time as compared to prior art processes. Moreover, the integrated deposition process of the present invention gives good fill characteristics while providing sufficient protection to underlying structures.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 22, 2003
    Applicant: CHARTERED SEMICONDUCTORS MANUFACTURED LIMITED
    Inventors: Guy Eristoff, Sarion C.S. Lee, Liew San Leong, Goh Khoon Meng