Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.

Abstract: Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

Abstract: Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.

Abstract: Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.

Abstract: Methods, systems, and computer programs are presented for implementing a network on chip (NOC). One programmable integrated circuit comprises a plurality of clusters, an internal network on chip (iNOC), and an external network on chip (eNOC) outside the plurality of clusters. The plurality of clusters is disposed on a plurality of cluster rows and a plurality of cluster columns, each cluster comprising programmable logic. Further, the iNOC comprises iNOC rows and iNOC columns. Each iNOC row is configured for transporting data and comprising connections to clusters in a cluster row and the eNOC, and each iNOC column is configured for transporting data and comprising connections to clusters in a cluster column and the eNOC.