Patents by Inventor Sarma V. R. K. V. Vangala

Sarma V. R. K. V. Vangala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9413672
    Abstract: The disclosed embodiments provide a system that processes network packets on an electronic device. During operation, the system obtains, on the electronic device, an outgoing rate of the network packets from a network interface queue on the electronic device to a network link. Next, upon detecting a transmission of the network packets from an application on the electronic device to the network interface queue, the system uses the electronic device to allocate a proportion of the outgoing rate to the application based on a number of applications transmitting network packets from the electronic device to the network link. Finally, the system uses the allocated proportion of the outgoing rate and the network interface queue to transmit network packets from the application to the network link.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: August 9, 2016
    Assignee: Apple Inc.
    Inventors: Sarma V. R. K. V. Vangala, Faraz Faheem, Vikram B. Yerrabommanahalli, Swaminathan Balakrishnan
  • Patent number: 8774190
    Abstract: An apparatus and method for efficiently decoding data received in the form of data packets is provided. The design includes at least one decoding unit configured to receive and decode multiple packet groups, each packet group comprising a plurality of data packets received over at least one wireless transmission channel; a buffer arrangement configured to collect complete and incomplete packet groups received over each wireless transmission channel, and a processor configured to direct data packets from the at least one decoding unit to specific locations in the buffer arrangement. The processor further inserts later received data packets into associated packet groups maintained in the buffer arrangement to minimize sequence gaps in the data packets. The design subsequently provides multiple packet groups and any later received data packets from the buffer arrangement to a resequencer.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: July 8, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Shanta P. Namburi, Pavan C. Kaivaram, Sarma V. R. K. V. Vangala
  • Publication number: 20130329556
    Abstract: The disclosed embodiments provide a system that processes network packets on an electronic device. During operation, the system obtains, on the electronic device, an outgoing rate of the network packets from a network interface queue on the electronic device to a network link. Next, upon detecting a transmission of the network packets from an application on the electronic device to the network interface queue, the system uses the electronic device to allocate a proportion of the outgoing rate to the application based on a number of applications transmitting network packets from the electronic device to the network link. Finally, the system uses the allocated proportion of the outgoing rate and the network interface queue to transmit network packets from the application to the network link.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Applicant: APPLE INC.
    Inventors: Sarma V. R. K. V. Vangala, Faraz Faheem, Vikram B. Yerrabommanahalli, Swaminathan Balakrishnan
  • Publication number: 20110194487
    Abstract: An apparatus and method for efficiently decoding data received in the form of data packets is provided. The design includes at least one decoding unit configured to receive and decode multiple packet groups, each packet group comprising a plurality of data packets received over at least one wireless transmission channel; a buffer arrangement configured to collect complete and incomplete packet groups received over each wireless transmission channel, and a processor configured to direct data packets from the at least one decoding unit to specific locations in the buffer arrangement. The processor further inserts later received data packets into associated packet groups maintained in the buffer arrangement to minimize sequence gaps in the data packets. The design subsequently provides multiple packet groups and any later received data packets from the buffer arrangement to a resequencer.
    Type: Application
    Filed: February 8, 2010
    Publication date: August 11, 2011
    Applicant: QUALCOMM Incorporated
    Inventors: Shanta P. Namburi, Pavan C. Kaivaram, Sarma V. R. K. V. Vangala