Patents by Inventor Sarosh I. Azad
Sarosh I. Azad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111693Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Krishnan SRINIVASAN, Ygal ARBEL, Sagheer AHMAD, Sarosh I. AZAD, Pramod BHARDWAJ, Yanran CHEN, James MURRAY
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Patent number: 11947409Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.Type: GrantFiled: January 12, 2022Date of Patent: April 2, 2024Assignee: XILINX, INC.Inventors: Sarosh I. Azad, Aditi R. Ganesan
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Publication number: 20230222026Abstract: An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.Type: ApplicationFiled: January 12, 2022Publication date: July 13, 2023Inventors: Sarosh I. AZAD, Aditi R. GANESAN
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Publication number: 20230085149Abstract: In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.Type: ApplicationFiled: September 16, 2021Publication date: March 16, 2023Inventors: Pramod BHARDWAJ, Sarosh I. AZAD, Wern-Yan KOE, Amitava MAJUMDAR
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Publication number: 20230059517Abstract: An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.Type: ApplicationFiled: August 18, 2021Publication date: February 23, 2023Inventors: Sarosh I. AZAD, Benson CHAU, Tomai KNOPP
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Patent number: 11581881Abstract: An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.Type: GrantFiled: August 18, 2021Date of Patent: February 14, 2023Assignee: XILINX, INC.Inventors: Sarosh I. Azad, Benson Chau, Tomai Knopp
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Patent number: 11429481Abstract: Embodiments herein describe a hardware based scrubbing scheme where correction logic is integrated with memory elements such that scrubbing is performed by hardware. The correction logic reads the data words stored in the memory element during idle cycles. If a correctable error is detected, the correction logic can then use a subsequent idle cycle to perform a write to correct the error (i.e., replace the corrupted data stored in the memory element with corrected data). By using built-in or integrated correction logic, the embodiments herein do not add extra work for the processor, or can work with applications that do not include a processor. Further, because the correction logic scrubs the memory during idle cycles, correcting bit errors does not have a negative impact on the performance of the memory element. Memory scrubbing can delay the degradation of data error, extending the integrity of the data in the memory.Type: GrantFiled: February 17, 2021Date of Patent: August 30, 2022Assignee: XILINX, INC.Inventors: Sarosh I. Azad, Wern-Yan Koe, Amitava Majumdar
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Patent number: 10657067Abstract: A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.Type: GrantFiled: September 12, 2016Date of Patent: May 19, 2020Assignee: Xilinx, Inc.Inventors: Sarosh I. Azad, Bhaarath Kumar
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Patent number: 10402332Abstract: Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.Type: GrantFiled: May 24, 2016Date of Patent: September 3, 2019Assignee: XILINX, INC.Inventors: Bhaarath Kumar, Sarosh I. Azad
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Patent number: 10042692Abstract: The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.Type: GrantFiled: September 29, 2015Date of Patent: August 7, 2018Assignee: XILINX, INC.Inventors: Sarosh I. Azad, Bhaarath Kumar, Tomai Knopp
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Patent number: 9965417Abstract: Techniques for communication with a host system via a peripheral component interconnect express (PCIe) communication fabric are disclosed herein. A peripheral device having its own memory address space executes a boot ROM to initialize a PCIe-to internal memory address space bridge and to disable MSIx interrupts. The peripheral device monitors a specific location in memory dedicated to MSIx interrupts for a particular value that indicates that PCIe device enumeration is complete. At this point, the peripheral device knows that its PCIe base address registers have been set by the host, and sets address translation registers for translating addresses in the address space of the host to the address space of the peripheral device.Type: GrantFiled: January 13, 2016Date of Patent: May 8, 2018Assignee: XILINX, INC.Inventors: Sarosh I. Azad, Sunita Jain
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Publication number: 20170344482Abstract: Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.Type: ApplicationFiled: May 24, 2016Publication date: November 30, 2017Applicant: Xilinx, Inc.Inventors: Bhaarath Kumar, Sarosh I. Azad
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Patent number: 9720868Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.Type: GrantFiled: July 7, 2014Date of Patent: August 1, 2017Assignee: XILINX, INC.Inventors: Ygal Arbel, Sagheer Ahmad, Sarosh I. Azad
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Patent number: 9465766Abstract: An apparatus for communication using a master-slave communication protocol includes a master circuit and a slave circuit configured to communicate with each other using a master-slave communication protocol. The apparatus also includes an interface circuit coupled to the master and slave circuits. In response to a first control signal having a first value, the interface circuit forwards messages received from the master circuit to the slave circuit and forwards responses received from the slave circuit to the master circuit. In response to the first control signal having a second value, the interface circuit prevents messages received from the master circuit from being forwarded from the master circuit to the slave circuit.Type: GrantFiled: October 29, 2013Date of Patent: October 11, 2016Assignee: XILINX, INC.Inventors: Tomai Knopp, Sarosh I. Azad, Bhaarath Kumar
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Patent number: 9411701Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.Type: GrantFiled: March 13, 2013Date of Patent: August 9, 2016Assignee: XILINX, INC.Inventor: Sarosh I. Azad
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Publication number: 20160004656Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.Type: ApplicationFiled: July 7, 2014Publication date: January 7, 2016Inventors: Ygal Arbel, Sagheer Ahmad, Sarosh I. Azad
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Patent number: 9148192Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.Type: GrantFiled: August 8, 2013Date of Patent: September 29, 2015Assignee: XILINX, INC.Inventors: Alan C. Wong, Christopher J. Borrelli, Loren Jones, Seu Wah Low, Parag Upadhyaya, Robert M. Ondris, Sarosh I. Azad
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Patent number: 8185678Abstract: A method and apparatus for controlling a data bus system is provided. A data bus system may use different hardware to perform transceiver and system control functions. The various embodiments of the invention increase compatibility of a data bus system with different transceiver hardware configurations by configuring the data transmission rate of the transceiver hardware at various points of operation to prevent or remedy several situations where the transceiver hardware may operate at a different data transmission rate than that used by the data bus system.Type: GrantFiled: June 19, 2009Date of Patent: May 22, 2012Assignee: Xilinx, Inc.Inventor: Sarosh I. Azad